参数资料
型号: ISL8101CRZ-T
厂商: Intersil
文件页数: 13/20页
文件大小: 0K
描述: IC CTRLR PWM BUCK 2PHASE 24-QFN
标准包装: 6,000
应用: 控制器,Intel VRM9,VRM10,AMD Hammer 应用
输入电压: 4.6 V ~ 12 V
输出数: 1
输出电压: 0.6 V ~ 2.3 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 24-VFQFN 裸露焊盘
供应商设备封装: 24-QFN(4x4)
包装: 带卷 (TR)
ISL8101
potential, the output drives are enabled, allowing the output
to ramp from the pre-charged level to the final level dictated
by the DAC setting. Should the output be pre-charged to a
level exceeding the DAC setting, the output drives are
enabled at the end of the soft-start period, leading to an
C 2
abrupt correction in the output voltage down to the DAC-set
level.
COMP
R 2
C 1
R 3
C 3
-
OUTPUT PRECHARGED
ABOVE DAC LEVEL
E/A
+
FB
R 1
V REF
OUTPUT PRECHARGED
BELOW DAC LEVEL
OSCILLATOR
V IN
V OUT
GND>
V OUT (0.5V/DIV)
PWM
CIRCUIT
V OSC
UGATE
L
D
HALF-BRIDGE
GND>
T1 T2
T3
ENLL (5V/DIV)
DRIVE
PHASE
LGATE
C
E
FIGURE 7. SOFT-START WAVEFORMS FOR ISL8101-BASED
MULTIPHASE CONVERTER
FREQUENCY COMPENSATION
ISL8101
EXTERNAL CIRCUIT
The ISL8101 multiphase converter behaves in a similar
manner to a voltage-mode controller. This section highlights
the design consideration for a voltage-mode controller requiring
external compensation. To address a broad range of
applications, a type-3 feedback network is recommended.
Figure 8 highlights the voltage-mode control loop for a
synchronous-rectified buck converter, applicable, with a small
number of adjustments, to the multiphase ISL8101 circuit. The
output voltage (V OUT ) is regulated to the reference voltage,
VREF, level. The error amplifier output (COMP pin voltage) is
compared with the oscillator (OSC) modified saw-tooth wave to
provide a pulse-width modulated wave with an amplitude of V IN
at the PHASE node. The PWM wave is smoothed by the output
filter (L and C). The output filter capacitor bank’s equivalent
series resistance is represented by the series resistor E.
FIGURE 8. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
The compensation network consists of the error amplifier
(internal to the ISL8101) and the external R 1 -R 3 , C 1 -C 3
components. The goal of the compensation network is to
provide a closed loop transfer function with high 0dB crossing
frequency (F 0 ; typically 0.1 to 0.3 of F SW ) and adequate phase
margin (better than 45°). Phase margin is the difference
between the closed loop phase at F 0dB and 180 ° . Equations
9,10, 11, and 12 relate the compensation network’s poles,
zeros and gain to the components (R 1 , R 2 , R 3 , C 1 , C 2 , and
C 3 ) (see Figure 8). Use the following guidelines for locating the
poles and zeros of the compensation network:
1. Select a value for R 1 (1k Ω to 5k Ω , typically). Calculate
value for R 2 for desired converter bandwidth (F 0 ).
V OSC ? R 1 ? F 0
d MAX ? V IN ? F LC
The modulator transfer function is the small-signal transfer
function of V OUT /V COMP . This function is dominated by a DC
gain, given by d MAX V IN /V OSC , and shaped by the output
R2 = ---------------------------------------------
(EQ. 9)
filter, with a double pole break frequency at F LC and a zero at
F CE . For the purpose of this analysis, L and D represent the
individual channel inductance and its DCR divided by 2
(equivalent parallel value of the two output inductors), while C
and E represents the total output capacitance and its
equivalent series resistance (see Equation 8).
2. Calculate C 1 such that F Z1 is placed at a fraction of the F LC ,
at 0.1 to 0.75 of F LC (to adjust, change the 0.5 factor to
desired number). The higher the quality factor of the output
filter and/or the higher the ratio F CE /F LC , the lower the F Z1
frequency (to maximize phase boost).
F LC = ---------------------------
F CE = ------------------------
C 1 = -----------------------------------------------
1
2 π ? L ? C
1
2 π ? C ? E
(EQ. 8)
1
2 π ? R 2 ? 0.5 ? F LC
(EQ. 10)
13
FN9223.1
July 28, 2008
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