参数资料
| 型号： | ISL8101CRZ-T |
| 厂商： | Intersil |
| 文件页数： | 6/20页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR PWM BUCK 2PHASE 24-QFN |
| 标准包装： | 6,000 |
| 应用： | 控制器，Intel VRM9，VRM10，AMD Hammer 应用 |
| 输入电压： | 4.6 V ~ 12 V |
| 输出数： | 1 |
| 输出电压： | 0.6 V ~ 2.3 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-VFQFN 裸露焊盘 |
| 供应商设备封装： | 24-QFN（4x4） |
| 包装： | 带卷 (TR) |
ISL8101
referenced to the GND pin. LGATE drive is referenced to the
PGND pin.
VID0-4 (Pins 2, 1, 24-22)
Voltage identification inputs from microprocessor. These pins
respond to TTL logic thresholds. The ISL8101 decodes the
VID inputs to establish the output voltage; see VID Tables
beginning on page 9 for correspondence between DAC codes
and output voltage settings. These pins are internally pulled
high, to approximately 1.2V, by 40μA (typically) internal
current sources; the internal pull-up current decrease to 0 as
the VID voltage approaches the internal pull-up voltage. All
VID pins are compatible with external pull-up voltages not
exceeding the IC’s bias voltage.
DACSEL/VID5 (Pin 3)
If VRM10 pin is grounded, DACSEL/VID5 represents the 6th
voltage identification input from the VRM10-compliant
microprocessor, otherwise known as VID5. If VRM10 pin is
open or pulled high, DACSEL/VID5 selects the compliance
standard for the internal DAC: pulled to ground it encodes the
DAC with AMD Hammer VID codes, while left open or pulled
high, it encodes the DAC with Intel VRM9.0 codes.
VRM10 (Pin 4)
This pin selects VRM10.0 DAC compliance when grounded.
Left open, it allows selection of either VRM9.0 or Hammer
DAC compliance via DACSEL pin.
ENLL (Pin 21)
This pin is a precision-threshold (approximately 0.6V) enable
pin. Held low, this pin disables controller operation. Pulled
high, the pin enables the controller for operation.
FB and COMP (Pins 6, 5)
The internal error amplifier ’s inverting input and output
where:
r DS(ON)MAX = lower MOSFET’s highest drain-source ON
resistance ( Ω ; include temperature effects)
I OUT = channel maximum output current (A)
See “Channel Balance Current Loop” on page 7 for more
information.
UGATE1, 2 (Pins 19, 12)
Connect these pins to the upper MOSFETs’ gates. These
pins are used to control the upper MOSFETs and are
monitored for shoot-through prevention purposes. Maximum
individual channel duty cycle is limited to 66%.
BOOT1, 2 (Pins 20, 11)
These pins provide the bias voltage for the upper MOSFETs’
drives. Connect these pins to appropriately-chosen external
bootstrap capacitors. Internal bootstrap diodes connected to
the PVCC pins provide the necessary bootstrap charge.
PHASE1, 2 (Pins 18, 13)
Connect these pins to the sources of the upper MOSFETs.
These pins are the return path for the upper MOSFETs’
drives.
LGATE1, 2 (Pins 17, 15)
These pins are used to control the lower MOSFETs and are
monitored for shoot-through prevention purposes. Connect
these pins to the lower MOSFETs’ gates.
OFS (Pin 9)
This pin is used to create an adjustable output voltage offset.
For no offset, leave this pin open. For negative offset, connect
a R’ OFS resistor from this pin to V CC and size it according to
Equation 2.
R ′ OFS = R 1 × --------------------------
V
respectively. These pins are connected to the external
network used to compensate the regulator ’s feedback loop.
1500
OFFSET
(EQ. 2)
An internal current source injects the offset (OFS) current
sampled into the FB pin. Pulling COMP to ground through an
impedance lower than 15 Ω disables the controller (same
effect as ENLL pulled low).
ISEN (Pin 7)
where:
V OFFSET = desired output voltage offset magnitude (mV)
For positive output voltage offset, connect a R OFS resistor
from this pin to GND, sizing it according to Equation 3.
R OFS = R 1 × --------------------------
V
This pin is used to close the current-balance loop and set the
overcurrent protection threshold. A resistor connected
between this pin and V CC has a voltage drop forced across it
500
OFFSET
(EQ. 3)
equal to that sampled across the lower MOSFET’s r DS(ON)
during approximately the middle of its conduction interval.
The resulting current through this resistor is used for channel
current balancing and overcurrent protection. The voltage
across the R ISEN resistor is time multiplexed between the
two channels.
To select the proper R ISEN resistor, use Equation 1.
For more information, refer to “Output Voltage Setting” on
page 9 .
SSEND (Pin 10)
This pin is an end of soft-start (SS) indicator; open drain
output device stays ON during soft-start, and goes open when
soft-start ends.
R ISEN = -------------------------------------------------------
r DS ( ON ) MAX × I OUT
95 μ A
6
(EQ. 1)
FN9223.1
July 28, 2008
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相关代理商/技术参数 |
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| ISL8101EVAL1 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Two-Phase Multiphase Buck PWM Controller with Integrated MOSFET Drivers |
| ISL8101IRZ | 功能描述:电压模式 PWM 控制器 W/ANNEAL P6 TWO PHS W/INT DRVRS GEN PURP RoHS:否 制造商:Texas Instruments 输出端数量:1 拓扑结构:Buck 输出电压:34 V 输出电流: 开关频率: 工作电源电压:4.5 V to 5.5 V 电源电流:600 uA 最大工作温度:+ 125 C 最小工作温度:- 40 C 封装 / 箱体:WSON-8 封装:Reel |
| ISL8101IRZ-T | 功能描述:电压模式 PWM 控制器 W/ANNEAL P6 TWO PHS W/INT DRVRS GEN PURP RoHS:否 制造商:Texas Instruments 输出端数量:1 拓扑结构:Buck 输出电压:34 V 输出电流: 开关频率: 工作电源电压:4.5 V to 5.5 V 电源电流:600 uA 最大工作温度:+ 125 C 最小工作温度:- 40 C 封装 / 箱体:WSON-8 封装:Reel |
| ISL8102 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Two-Phase Buck PWM Controller with High Current Integrated MOSFET Drivers |
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