参数资料
| 型号： | ISL8101CRZ-T |
| 厂商： | Intersil |
| 文件页数： | 14/20页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR PWM BUCK 2PHASE 24-QFN |
| 标准包装： | 6,000 |
| 应用： | 控制器，Intel VRM9，VRM10，AMD Hammer 应用 |
| 输入电压： | 4.6 V ~ 12 V |
| 输出数： | 1 |
| 输出电压： | 0.6 V ~ 2.3 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-VFQFN 裸露焊盘 |
| 供应商设备封装： | 24-QFN（4x4） |
| 包装： | 带卷 (TR) |
ISL8101
2 π ? R 2 ? C 1 ? F CE – 1
3. Calculate C 2 such that F P1 is placed at F CE .
C 1
C 2 = --------------------------------------------------------
(EQ. 11)
F Z1 F Z2
F P1
F P2
MODULATOR GAIN
COMPENSATION GAIN
CLOSED LOOP GAIN
OPEN LOOP E/A GAIN
4. Calculate R 3 (see Equation 12) such that F Z2 is placed at
? R 2 ?
OSC
F LC . Calculate C 3 such that F P2 is placed below F SW
(typically, 0.5 to 1.0 times F SW ). F SW represents the
per-channel switching frequency. Change the numerical
factor to reflect desired placement of this pole. Placement
of F P2 lower in frequency helps reduce the gain of the
compensation network at high frequency, in turn reducing
0
20 log ? ------- ?
? R 2 ?
d MAX ? V IN
20 log ---------------------------------
V
G CL
G FB
the HF ripple component at the COMP pin and minimizing
resultant duty cycle jitter.
G MOD
R 3 = ----------------------
F SW
FREQUENCY
F CE
F LC
F 0
C 3 = -------------------------------------------------
R 1
------------ – 1
F LC
1
2 π ? R 3 ? 0.7 ? F SW
(EQ. 12)
LOG
FIGURE 9. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
compensation transfer function and then plotting the resulting
gain.
It is recommended a mathematical model is used to plot the
G MOD ( f ) = ------------------------------ ? ----------------------------------------------------------------------------------------
V OSC
1 + s ( f ) ? ( E + D ) ? C + s ( f ) ? L ? C
G FB ( f ) = ---------------------------------------------------- ?
1 + s ( f ) ? R 2 ? C 1
s ( f ) ? R 1 ? ( C 1 + C 2 )
1 + s ( f ) ? ( R 1 + R 3 ) ? C 3
( 1 + s ( f ) ? R 3 ? C 3 ) ? ? 1 + s ( f ) ? R 2 ? ? --------------------- ? ?
loop response. Check the loop gain against the error
amplifier ’s open-loop gain. Verify phase margin results and
adjust as necessary. Equations 13 and 14 describe the
frequency response of the modulator (G MOD ), feedback
compensation (G FB ) and closed-loop response (G CL ):
d MAX ? V IN 1 + s ( f ) ? E ? C
2
(EQ. 13)
? -------------------------------------------------------------------------------------------------------------------------
? ? C 1 ? C 2 ? ?
? ? C 1 + C 2 ? ?
G CL ( f ) = G MOD ( f ) ? G FB ( f ) where , s ( f ) = 2 π ? f ? j
COMPENSATION BREAK FREQUENCY EQUATIONS
A stable control loop has a gain crossing with close to a
-20dB/decade slope and a phase margin greater than 45°.
Include worst case component variations when determining
phase margin. The mathematical model presented makes a
number of approximations and is generally not accurate at
frequencies approaching or exceeding half the switching
frequency. When designing compensation networks, select
target crossover frequencies in the range of 10% to 30% of
the per-channel switching frequency, F SW .
General Application Design Guide
This design guide is intended to provide a high-level
explanation of the steps necessary to create a multiphase
power converter. It is assumed that the reader is familiar with
many of the basic skills and techniques referenced below. In
addition to this guide, Intersil provides complete reference
designs that include schematics, bills of materials, and
example board layouts for all common microprocessor
F Z1 = -------------------------------
F P1 = ---------------------------------------------
C 1 ? C 2
F Z2 = -------------------------------------------------
F P2 = -------------------------------
1
2 π ? R 2 ? C 1
1
2 π ? ( R 1 + R 3 ) ? C 3
1
2 π ? R2 ? ---------------------
C 1 + C 2
1
2 π ? R 3 ? C 3
(EQ. 14)
applications.
MOSFETs
Given the fixed switching frequency of the ISL8101 and the
integrated output drives, the selection of MOSFETs revolves
closely around the current each MOSFET is required to
Figure 9 shows an asymptotic plot of the DC/DC converter’s
gain vs. frequency. The actual Modulator Gain has a high gain
peak dependent on the quality factor (Q) of the output filter,
which is not shown. Using the above guidelines should yield a
compensation gain similar to the curve plotted. The open loop
error amplifier gain bounds the compensation gain. Check the
compensation gain at F P2 against the capabilities of the error
amplifier. The closed loop gain, G CL , is constructed on the
log-log graph of Figure 9 by adding the modulator gain, G MOD
(in dB), to the feedback compensation gain, G FB (in dB). This is
equivalent to multiplying the modulator transfer function and the
14
conduct, the capability of the devices to dissipate heat, as well
as the characteristics of available heat sinking. Since the
ISL8101 drives the MOSFETs with 5V, the selection of
appropriate MOSFETs should be done by comparing and
evaluating their characteristics at this specific V GS bias
voltage.
LOWER MOSFET POWER CALCULATION
Since virtually all of the heat loss in the lower MOSFET is
conduction loss (due to current conducted through the
channel resistance, r DS(ON) ), a quick approximation for heat
FN9223.1
July 28, 2008
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相关代理商/技术参数 |
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| ISL8101EVAL1 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Two-Phase Multiphase Buck PWM Controller with Integrated MOSFET Drivers |
| ISL8101IRZ | 功能描述:电压模式 PWM 控制器 W/ANNEAL P6 TWO PHS W/INT DRVRS GEN PURP RoHS:否 制造商:Texas Instruments 输出端数量:1 拓扑结构:Buck 输出电压:34 V 输出电流: 开关频率: 工作电源电压:4.5 V to 5.5 V 电源电流:600 uA 最大工作温度:+ 125 C 最小工作温度:- 40 C 封装 / 箱体:WSON-8 封装:Reel |
| ISL8101IRZ-T | 功能描述:电压模式 PWM 控制器 W/ANNEAL P6 TWO PHS W/INT DRVRS GEN PURP RoHS:否 制造商:Texas Instruments 输出端数量:1 拓扑结构:Buck 输出电压:34 V 输出电流: 开关频率: 工作电源电压:4.5 V to 5.5 V 电源电流:600 uA 最大工作温度:+ 125 C 最小工作温度:- 40 C 封装 / 箱体:WSON-8 封装:Reel |
| ISL8102 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Two-Phase Buck PWM Controller with High Current Integrated MOSFET Drivers |
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