参数资料
型号: ISL8102EVAL1
厂商: Intersil
文件页数: 11/27页
文件大小: 0K
描述: EVAL BOARD 1 FOR ISL8102
标准包装: 1
系列: *
ISL8102
I n = I L ? ----------------------
transition low. During this time the current sense amplifier
uses the ISEN inputs to reproduce a signal proportional to
the inductor current, I L . This sensed current, I SEN , is simply
a scaled version of the inductor current. The sample window
opens exactly 1/6 of the switching period, t SW , after the
PWM transitions low. The sample window then stays open
the rest of the switching cycle until PWM transitions high
again, as illustrated in Figure 4.
The sampled current, at the end of the t SAMPLE , is
proportional to the inductor current and is held until the next
switching period sample. The sampled current is used only
for channel current balance.
I L
PWM
SWITCHING PERIOD
I SEN
SAMPLING PERIOD
The ISL8102 senses the channel load current by sampling
the voltage across the lower MOSFET r DS(ON) , as shown in
Figure 5. A ground-referenced operational amplifier, internal
to the ISL8102, is connected to the PHASE node through a
resistor, R ISEN . The voltage across R ISEN is equivalent to
the voltage drop across the r DS(ON) of the lower MOSFET
while it is conducting. The resulting current into the ISEN pin
is proportional to the channel current, I L . The ISEN current is
sampled and held as described in “Current Sampling” on
page 10. From Figure 5, Equation 3 for I n is derived where I L
r DS ( ON )
(EQ. 3)
R ISEN
is the channel current.
Output Voltage Setting
The ISL8102 uses a digital to analog converter (DAC) to generate
a reference voltage based on the logic signals at the REF0 and
REF1 pins. The DAC decodes the 2-bit logic signals into one of the
discrete voltages shown in Table 1. Each REF0 and REF1 pins
are pulled up to an internal 1.2V voltage by weak current sources
(40μA current, decreasing to 0 as the voltage at the REF0, REF1
pins varies from 0 to the internal 1.2V pull-up voltage). External
pull-up resistors or active-high output stages can augment the pull-
up current sources, up to a voltage of 5V. The DAC pin must be
connected to REF pin through a 1kW to 5kW resistor and a filter
OLD SAMPLE
CURRENT
NEW SAMPLE
CURRENT
capacitor (0.022μF) is connected between REF and GND.
The ISL8102 accommodates the use of external voltage reference
TIME
FIGURE 4. SAMPLE AND HOLD TIMING
The ISL8102 supports MOSFET r DS(ON) current sensing to
sample each channel’s current for channel current balance.
The internal circuitry, shown in Figure 5 represents Channel
N of an N-channel converter. This circuitry is repeated for
each channel in the converter, but may not be active
depending on the status of the 2PH pin, as described in
V IN
connected to REF pin if a different output voltage is required. The
DAC voltage must be set at least as high as external reference.
The error amp internal non inverting input is the lower of REF or
(DAC +300mV).
A third method for setting the output voltage is to use a resistor
divider (R P1 , R S1 ) from the output terminal (V OUT ) to VSEN pin to
set the output voltage level as shown in Figure 6. This method is
good for generating voltages up to 2.3V (with the REF voltage set
to 1.5V).
For this case, the output voltage can be obtained as shown in
Equation 4.
SEN = I L x --------------------------
V OUT = V REF ? ---------------------------------- +? V OFS – V DROOP
R
I n
I
r DS ( ON )
R ISEN
CHANNEL N
UPPER MOSFET
( R S1 + R P1 )
P1
(EQ. 4)
SAMPLE
&
HOLD
-
+
ISEN(n)
R ISEN
CHANNEL N
LOWER MOSFET
I L
-
I L x r DS ( ON )
+
It is recommended to choose resistor values of less than
500 Ω for R S1 and R P1 resistors in order to get better output
voltage DC accuracy.
TABLE 1. ISL8102 DAC VOLTAGE SELECTION TABLE
REF1 REF0 DAC
0
0
0.600V
ISL8102 INTERNAL CIRCUIT
EXTERNAL CIRCUIT
0
1
0.900V
FIGURE 5. ISL8102 INTERNAL AND EXTERNAL CURRENT-
1
0
1.200V
SENSING CIRCUITRY FOR CURRENT BALANCE
11
1
1
1.500V
FN9247.1
July 28, 2008
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