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| 型号： | ISL8102EVAL1 |
| 厂商： | Intersil |
| 文件页数： | 23/27页 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD 1 FOR ISL8102 |
| 标准包装： | 1 |
| 系列： | * |
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ISL8102
compensation gain at F P2 against the capabilities of the error
amplifier. The closed loop gain, G CL , is constructed on the
log-log graph of Figure 23 by adding the modulator gain,
G MOD (in dB), to the feedback compensation gain, G FB (in
dB). This is equivalent to multiplying the modulator transfer
function and the compensation transfer function and then
plotting the resulting gain.
initially deviate by an amount approximated by the voltage
drop across the ESL. As the load current increases, the
voltage drop across the ESR increases linearly until the load
current reaches its final value. The capacitors selected must
have sufficiently low ESL and ESR so that the total
output-voltage deviation is less than the allowable maximum.
Neglecting the contribution of inductor current and regulator
response, the output voltage initially deviates by an amount
Δ V ≈ ( ESL ) ? ----- + ( ESR ) ? Δ I
F Z1 F Z2
F P1
F P2
MODULATOR GAIN
COMPENSATION GAIN
CLOSED LOOP GAIN
OPEN LOOP E/A GAIN
as shown in Equation 36.
di
dt
(EQ. 36)
The filter capacitor must have sufficiently low ESL and ESR
so that Δ V < Δ V MAX .
20 log ? -------- ?
0
R2
? R1 ?
d MAX ? V IN
20 log ---------------------------------
V OSC
G FB
Most capacitor solutions rely on a mixture of high frequency
capacitors with relatively low capacitance in combination
with bulk capacitors having high capacitance but limited
G CL
G MOD
high-frequency performance. Minimizing the ESL of the
high-frequency capacitors allows them to support the output
voltage as the current increases. Minimizing the ESR of the
LOG
F LC
F CE
F 0
FREQUENCY
bulk capacitors allows them to supply the increased current
with less output voltage deviation.
IN – N ? V OUT ? V OUT
? V ?
L ≥ ( ESR ) --------------------------------------------------------------------
FIGURE 23. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
A stable control loop has a gain crossing with close to a
-20dB/decade slope and a phase margin greater than 45°.
Include worst case component variations when determining
phase margin. The mathematical model presented makes a
number of approximations and is generally not accurate at
frequencies approaching or exceeding half the switching
frequency. When designing compensation networks, select
target crossover frequencies in the range of 10% to 30% of
the per-channel switching frequency, F sw .
Output Filter Design
The output inductors and the output capacitor bank together
to form a low-pass filter responsible for smoothing the
pulsating voltage at the phase nodes. The output filter also
must provide the transient energy until the regulator can
respond. Because it has a low bandwidth compared to the
switching frequency, the output filter limits the system
transient response. The output capacitors must supply or
sink load current while the current in the output inductors
increases or decreases to meet the demand.
In high-speed converters, the output capacitor bank is usually
the most costly (and often the largest) part of the circuit.
Output filter design begins with minimizing the cost of this part
of the circuit. The critical load parameters in choosing the
output capacitors are the maximum size of the load step, Δ I,
the load-current slew rate, di/dt, and the maximum allowable
The ESR of the bulk capacitors also creates the majority of
the output-voltage ripple. As the bulk capacitors sink and
source the inductor ac ripple current (see “Interleaving” on
capacitor ESR equal to I C,PP (ESR). Thus, once the output
capacitors are selected, the maximum allowable ripple
voltage, V PP(MAX) , determines the lower limit on the
inductance.
? ? (EQ. 37)
F SW ? V IN ? V PP ( MAX )
Since the capacitors are supplying a decreasing portion of the load
current while the regulator recovers from the transient, the
capacitor voltage becomes slightly depleted. The output inductors
must be capable of assuming the entire load current before the
output voltage decreases more than Δ V MAX . This places an upper
limit on inductance.
Equation 38 gives the upper limit on L for the cases when the
trailing edge of the current transient causes a greater output-
voltage deviation than the leading edge. Equation 39 addresses
the leading edge. Normally, the trailing edge dictates the selection
of L because duty cycles are usually less than 50%. Nevertheless,
both inequalities should be evaluated, and L should be selected
based on the lower of the two results. In each equation, L is the
per-channel inductance, C is the total output capacitance, and N is
the number of active channels.
L ≤ --------------------------------- ? Δ V MAX – ( Δ I ? ESR )
L ≤ ---------------------------------- ? Δ V MAX – ( Δ I ? ESR ) ? ? V IN – V O ?
( Δ I ) 2
output-voltage deviation under transient loading, Δ V MAX .
Capacitors are characterized according to their capacitance,
ESR, and ESL (equivalent series inductance).
At the beginning of the load transient, the output capacitors
supply all of the transient current. The output voltage will
23
2 ? N ? C ? V O
( Δ I ) 2
( 1.25 ) ? N ? C
? ?
(EQ. 38)
(EQ. 39)
FN9247.1
July 28, 2008
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