- 您现在的位置：买卖IC网 > PDF目录20672 > ISL8102EVAL1 (Intersil)EVAL BOARD 1 FOR ISL8102 PDF资料下载
参数资料
| 型号： | ISL8102EVAL1 |
| 厂商： | Intersil |
| 文件页数： | 14/27页 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD 1 FOR ISL8102 |
| 标准包装： | 1 |
| 系列： | * |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页当前第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页
ISL8102
Advanced Adaptive Zero Shoot-Through Deadtime
Control (Patent Pending)
The integrated drivers incorporate a unique adaptive deadtime
control technique to minimize deadtime, resulting in high
efficiency from the reduced freewheeling time of the lower
MOSFET body-diode conduction, and to prevent the upper and
lower MOSFETs from conducting simultaneously. This is
accomplished by ensuring either rising gate turns on its
MOSFET with minimum and sufficient delay after the other has
1.6
1.4
1.2
1.
0.8
turned off.
During turn-off of the lower MOSFET, the PHASE voltage is
0.6
0.4
Q GATE = 100nC
monitored until it reaches a -0.3V/+0.8V trip point for a
forward/reverse current, at which time the UGATE is released
0.2
20nC
50nC
to rise. An auto-zero comparator is used to correct the r DS(ON)
drop in the phase voltage preventing false detection of the
-0.3V phase level during r DS(ON) conduction period. In the
0.0
0.0
0.1
0.2
0.3
0.4 0.5 0.6
Δ V BOOT_CAP (V)
0.7
0.8
0.9
1.0
case of zero current, the UGATE is released after 35ns delay of
the LGATE dropping below 0.5V. During the phase detection,
the disturbance of LGATE falling transition on the PHASE node
is blanked out to prevent falsely tripping. Once the PHASE is
high, the advanced adaptive shoot-through circuitry monitors
the PHASE and UGATE voltages during a PWM falling edge
and the subsequent UGATE turn-off. If either the UGATE falls
to less than 1.75V above the PHASE or the PHASE falls to less
than +0.8V, the LGATE is released to turn on.
Internal Bootstrap Device
The two integrated drivers feature an internal bootstrap
schottky diode. Simply adding an external capacitor across
the BOOT and PHASE pins completes the bootstrap circuit.
The bootstrap function is also designed to prevent the
bootstrap capacitor from overcharging due to the large
negative swing at the PHASE node. This reduces voltage
stress on the boot to phase pins.
The bootstrap capacitor must have a maximum voltage
rating above PVCC + 5V and its capacitance value can be
chosen from Equation 11.
FIGURE 10. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE
VOLTAGE
Gate Drive Voltage Versatility
The ISL8102 provides the user flexibility in choosing the
gate drive voltage for efficiency optimization. The controller
ties the upper and lower drive rails together. Simply applying
a voltage from 5V up to 12V on PVCC sets both gate drive
rail voltages simultaneously.
Initialization
Prior to initialization, proper conditions must exist on the
ENLL, VCC, PVCC and the REF0 and REF1 pins. When the
conditions are met, the controller begins soft-start. Once the
output voltage is within the proper window of operation, the
controller asserts PGOOD.
Enable and Disable
While in shutdown mode, the PWM outputs are held in a
high-impedance state to assure the drivers remain off. The
following input conditions must be met before the ISL8102 is
released from shutdown mode.
C BOOT_CAP ≥ --------------------------------------
Q GATE = ---------------------------------- ? N Q1
Q GATE
Δ V BOOT_CAP
Q G1 ? PVCC
V GS1
(EQ. 11)
1. The bias voltage applied at VCC must reach the internal
power-on reset (POR) rising threshold. Once this
threshold is reached, proper operation of all aspects of
the ISL8102 is guaranteed. Hysteresis between the rising
and falling thresholds assure that once enabled, the
ISL8102 will not inadvertently turn off unless the bias
where Q G1 is the amount of gate charge per upper MOSFET
at V GS1 gate-source voltage and N Q1 is the number of
control MOSFETs. The Δ V BOOT_CAP term is defined as the
allowable droop in the rail of the upper gate drive. Figure 10
shows the boot capacitor ripple voltage as a function of boot
capacitor value and total upper MOSFET gate charge.
14
voltage drops substantially (see “Electrical
Specifications” on page 5).
FN9247.1
July 28, 2008
相关PDF资料 |
PDF描述 |
|---|---|
| T95S685M6R3HSAL | CAP TANT 6.8UF 6.3V 20% 1507 |
| VI-J63-CX-F3 | CONVERTER MOD DC/DC 24V 75W |
| F951D106KBAAQ2 | CAP TANT 10UF 20V 10% 1210 |
| TTN2.00SV50 | 2" THERMASHIELD TUBE SILVER 50' |
| MAX4210BEUA+T | IC CURRENT MONITOR 1.5% 8MSOP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL8102IRZ | 功能描述:IC REG CTRLR BUCK PWM VM 32-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:500kHz 占空比:100% 电源电压:8.2 V ~ 30 V 降压:无 升压:无 回扫:是 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:0°C ~ 70°C 封装/外壳:8-DIP（0.300"，7.62mm） 包装:管件 产品目录页面:1316 (CN2011-ZH PDF) |
| ISL8102IRZ-T | 功能描述:IC REG CTRLR BUCK PWM VM 32-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:500kHz 占空比:100% 电源电压:8.2 V ~ 30 V 降压:无 升压:无 回扫:是 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:0°C ~ 70°C 封装/外壳:8-DIP（0.300"，7.62mm） 包装:管件 产品目录页面:1316 (CN2011-ZH PDF) |
| ISL8103 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Three-Phase Buck PWM Controller with High Current Integrated MOSFET Drivers |
| ISL8103CRZ | 功能描述:IC REG CTRLR BUCK PWM VM 40-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:500kHz 占空比:100% 电源电压:8.2 V ~ 30 V 降压:无 升压:无 回扫:是 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:0°C ~ 70°C 封装/外壳:8-DIP（0.300"，7.62mm） 包装:管件 产品目录页面:1316 (CN2011-ZH PDF) |
| ISL8103CRZ-T | 功能描述:IC REG CTRLR BUCK PWM VM 40-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:500kHz 占空比:100% 电源电压:8.2 V ~ 30 V 降压:无 升压:无 回扫:是 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:0°C ~ 70°C 封装/外壳:8-DIP（0.300"，7.62mm） 包装:管件 产品目录页面:1316 (CN2011-ZH PDF) |
发布紧急采购，3分钟左右您将得到回复。