参数资料
型号: ISL8104EVAL2Z
厂商: Intersil
文件页数: 6/14页
文件大小: 0K
描述: EVAL BOARD 2 FOR ISL8104
标准包装: 1
系列: *
ISL8104
LX (Pin 7/8)
This pin connects to the source of the top-side MOSFET and
the drain of the bottom-side MOSFET. This pin represents
the return path for the top-side gate driver. During normal
switching, this pin is used for top-side current sensing.
1000
R FSET PULLUP
TO VCC
TGATE (Pin 8/9)
Connect TGATE to the top-side MOSFET gate. This pin
provides the gate drive for the top-side MOSFET.
BOOT (Pin 9/10)
This pin provides bias to the top-side MOSFET driver. A
bootstrap circuit may be used to create a BOOT voltage
100
10
R FSET PULL-DOWN
TO GND
suitable to drive a standard N-Channel MOSFET.
10k
100k
1M
SWITCHING FREQUENCY (Hz)
PGND (Pin 10/11)
This is the power ground connection. Tie the bottom-side
MOSFET source and board ground to this pin.
BGATE (Pin 11/12)
80
70
FIGURE 1. R FSET RESISTANCE vs FREQUENCY
Connect BGATE to the bottom-side MOSFET gate. This pin
provides the gate drive for the bottom-side MOSFET.
PVCC (Pin 12/13)
60
50
40
C GATE = 3300pF
C GATE = 1000pF
Provide an 8V to 14V bias supply for the bottom-side gate
drive to this pin. This pin should be bypassed with a
capacitor to PGND.
30
20
VCC (Pin 13/14)
10
C GATE = 10pF
Provide an 8V to 14V bias supply for the chip to this pin. The
pin should be bypassed with a capacitor to GND.
FSET (Pin 14/1)
This pin provides oscillator switching frequency adjustment.
By placing a resistor (R FSET ) from this pin to GND, the
switching frequency is set from between 200kHz and
1.5MHz according to Equation 1:
0
100k 200k 300k 400k 500k 600k 700k 800k 900k 1M
SWITCHING FREQUENCY (Hz)
FIGURE 2. BIAS SUPPLY CURRENT vs FREQUENCY
SSDONE (QFN ONLY Pin 16)
Provides an open drain signal at the end of soft-start.
R FSET [ k Ω ] ≈ ? ------------------------------------------------------- – 1.3 ? k Ω
? F [ kHz ] – 200 [ kHz ] ?
s
6500
(R FSET to GND)
(EQ. 1)
Functional Description
Initialization
The ISL8104 automatically initializes upon receipt of power.
Alternately ISL8104’s switching frequency can be lowered
from 200kHz to 50kHz by connecting the FSET pin with a
resistor to VCC according Equation 2:
Special sequencing of the input supplies is not necessary.
The Power-On Reset (POR) function continually monitors
the bias voltage at the VCC pin and the driver input on the
R FSET [ k Ω ] ≈ ? ------------------------------------------------------- + 70 ? k Ω
? 200 [ kHz ] – F [ kHz ] ?
55000
s
(R FSET to VCC)
PVCC pin. When the voltages at VCC and PVCC exceed
their rising POR thresholds, a 30μA current source driving
(EQ. 2)
TSOC (Pin 15/2)
The current limit is programmed by connecting this pin with a
resistor and capacitor to the drain of the top-side MOSEFT.
A 200μA current source develops a voltage across the
resistor which is then compared with the voltage developed
across the top-side MOSFET. A blanking period of 120ns is
provided for noise immunity.
6
the SS pin is enabled. Upon the SS pin exceeding 1V, the
ISL8104 begins ramping the non-inverting input of the error
amplifier from GND to the System Reference. During
initialization the MOSFET drivers pull TGATE to LX and
BGATE to PGND.
Soft-Start
During soft-start, an internal 30μA current source charges the
external capacitor (C SS ) on the SS pin up to ~4V. If the
ISL8104 is utilizing the internal reference, then as the SS pin’s
voltage ramps from 1V to 3V, the soft-start function scales the
FN9257.2
March 7, 2008
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