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参数资料
| 型号： | ISL8104EVAL2Z |
| 厂商： | Intersil |
| 文件页数： | 9/14页 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD 2 FOR ISL8104 |
| 标准包装： | 1 |
| 系列： | * |
ISL8104
The power plane should support the input power and output
power nodes. Use copper filled polygons on the top and
bottom circuit layers for the LX nodes. Use the remaining
printed circuit layers for small signal wiring.
Locate the ISL8104 within 2 to 3 inches of the MOSFETs, Q 1
and Q 2 (1 inch or less for 500kHz or higher operation). The
circuit traces for the MOSFETs’ gate and source connections
from the ISL8104 must be sized to handle up to 3A peak
current. Minimize any leakage current paths on the SS pin and
locate the capacitor, C ss close to the SS pin as the internal
current source is only 30μA. Provide local V CC decoupling
between VCC and GND pins. Locate the capacitor, C BOOT as
close as practical to the BOOT pin and the phase node.
Compensating the Converter
Figure 7 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage is
regulated to the reference voltage level. The error amplifier
output is compared with the oscillator triangle wave to
provide a pulse-width modulated wave with an amplitude of
V IN at the LX node. The PWM wave is smoothed by the
output filter. The output filter capacitor bank’s equivalent
series resistance is represented by the series resistor ESR.
The modulator transfer function is the small-signal transfer
function of V OUT /V COMP . This function is dominated by a
DC gain and shaped by the output filter, with a double pole
break frequency at F LC and a zero at F CE . For the purpose
of this analysis, L and DCR represent the output inductance
and its DCR, while C and ESR represents the total output
capacitance and its equivalent series resistance.
F LC = ---------------------------
F CE = ---------------------------------
This section highlights the design consideration for a voltage
mode controller requiring external compensation. To address a
1
2 π ? L ? C
1
2 π ? C ? ESR
(EQ. 7)
broad range of applications, a type-3 feedback network is
recommended (see Figure 6).
C 2
The compensation network consists of the error amplifier
(internal to the ISL8104) and the external R 1 to R 3 , C 1 to C 3
components. The goal of the compensation network is to
R 2
C 1
COMP
provide a closed loop transfer function with high 0dB crossing
frequency (F 0 ; typically 0.1 to 0.3 of f SW ) and adequate phase
margin (better than 45°). Phase margin is the difference
C 3
FB
between the closed loop phase at F 0dB and 180°. The
R 3
R 1
VOUT
ISL8104
equations that follow relate the compensation network’s poles,
zeros and gain to the components (R 1 , R 2 , R 3 , C 1 , C 2 , and
C 3 ) in Figures 6 and 7. Use the following guidelines for
locating the poles and zeros of the compensation network:
FIGURE 6. COMPENSATION CONFIGURATION FOR THE
ISL8104 CIRCUIT
C 2
1. Select a value for R 1 (1k Ω to 10k Ω , typically). Calculate
value for R 2 for desired converter bandwidth (F 0 ). If
setting the output voltage to be equal to the reference set
voltage as shown in Figure 7, the design procedure can
be followed as presented in Equation 8.
D MAX ? V IN ? F LC
COMP
R 2
C 1
R 3
C 3
V OSC ? R 1 ? F 0
R 2 = ----------------------------------------------
(EQ. 8)
V IN ? F LC
E/A
-
+
VREF
FB
GND
R 1
As the ISL8104 supports 100% duty cycle, D MAX equals 1.
The ISL8104 uses a fixed ramp amplitude (V OSC ) of 1.9V,
Equation 8 simplifies to Equation 9:
1.9 ? R 1 ? F 0
R 2 = -------------------------------
(EQ. 9)
2. Calculate C 1 such that F Z1 is placed at a fraction of the F LC ,
at 0.1 to 0.75 of F LC (to adjust, change the 0.5 factor in
OSCILLATOR
V IN
V OUT
Equation 10 to the desired number). The higher the quality
factor of the output filter and/or the higher the ratio
(EQ. 10)
C 1 = -----------------------------------------------
PWM
CIRCUIT
V OSC
HALF-BRIDGE
DRIVE
TGATE
LX
L
DCR
C
F CE /F LC , the lower the F Z1 frequency (to maximize
phase boost at F LC ).
1
2 π ? R 2 ? 0.5 ? F LC
2 π ? R 2 ? C 1 ? F CE – 1
ISL8104
ESR
BGATE
EXTERNAL CIRCUIT
3. Calculate C 2 such that F P1 is placed at F CE .
C 1
C 2 = --------------------------------------------------------
(EQ. 11)
FIGURE 7. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
9
4. Calculate R 3 such that F Z2 is placed at F LC . Calculate C 3
such that F P2 is placed below f SW (typically, 0.3 to 1.0
FN9257.2
March 7, 2008
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL8104IBZ | 功能描述:IC REG CTRLR BUCK PWM VM 14-SOIC RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
| ISL8104IBZ | 制造商:Intersil Corporation 功能描述:Pulse Width Modulation (PWM) Controller |
| ISL8104IBZ-T | 功能描述:IC REG CTRLR BUCK PWM VM 14-SOIC RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
| ISL8104IRZ | 功能描述:IC REG CTRLR BUCK PWM VM 16-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
| ISL8104IRZ-T | 功能描述:IC REG CTRLR BUCK PWM VM 16-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
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