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参数资料
| 型号： | ISL8112IRZ-T |
| 厂商： | Intersil |
| 文件页数： | 18/27页 |
| 文件大小： | 0K |
| 描述： | IC REG DL BCK/LINEAR SYNC 32-QFN |
| 标准包装： | 6,000 |
| 拓扑： | 降压（降压）同步（1），线性（LDO）（1） |
| 功能： | 任何功能 |
| 输出数： | 2 |
| 频率 - 开关： | 可调式 |
| 电压/电流 - 输出 1： | 控制器 |
| 电压/电流 - 输出 2： | 0.7 V ~ 4.5 V，200mA |
| 带 LED 驱动器： | 无 |
| 带监控器： | 无 |
| 带序列发生器： | 无 |
| 电源电压： | 4.5 V ~ 25 V |
| 工作温度： | -40°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘 |
| 供应商设备封装： | 32-QFN（5x5） |
| 包装： | 带卷 (TR) |
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ISL8112
DETECTION
higher inductor values include larger physical size and
degraded load-transient response (especially at low
input-voltage levels).
DC output accuracy specifications refer to the trip level of the
error comparator. When the inductor is in continuous
conduction, the output voltage has a DC regulation higher
than the trip level by 50% of the ripple. In discontinuous
conduction (MODE = GND, light load), the output voltage
has a DC regulation higher than the trip level by
approximately 1.0% due to slope compensation.
Forced-PWM Mode
The low-noise, forced-PWM (MODE = VCC) mode disables
the zero-crossing comparator, which controls the low-side
switch on-time. Disabling the zero-crossing detector causes
the low-side, gate-drive waveform to become the
complement of the high-side, gate-drive waveform. The
inductor current reverses at light loads as the PWM loop
strives to maintain a duty ratio of V OUT / V IN . The benefit of
forced-PWM mode is to keep the switching frequency fairly
constant, but it comes at a cost: the no-load battery current
can be 10mA to 50mA, depending on switching frequency
and the external MOSFETs.
Forced-PWM mode is most useful for reducing
audio-frequency noise, improving load-transient response,
providing sink-current capability for dynamic output voltage
adjustment, and improving the cross-regulation of
multiple-output applications that use a flyback transformer or
coupled inductor.
Enhanced Ultrasonic Mode
(25kHz (min) Pulse Skipping)
Leaving MODE unconnected or connecting MODE to
VREF1 activates a unique pulse-skipping mode with a
minimum switching frequency of 25kHz. This ultrasonic
pulse-skipping mode eliminates audio-frequency modulation
that would otherwise be present when a lightly loaded
controller automatically skips pulses. In ultrasonic mode, the
controller automatically transitions to fixed-frequency PWM
operation when the load reaches the same critical
conduction point (ILOAD(SKIP)).
An ultrasonic pulse occurs when the controller detects that
no switching has occurred within the last 20μs. Once
triggered, the ultrasonic controller pulls LG high, turning on
the low-side MOSFET to induce a negative inductor current.
After FB drops below the regulation point, the controller turns
off the low-side MOSFET (LG pulled low) and triggers a
constant on-time (UG driven high). When the on-time has
expired, the controller re-enables the low-side MOSFET until
the controller detects that the inductor current dropped
below the zero-crossing threshold. Starting with a LG pulse
greatly reduces the peak output voltage when compared to
starting with a UG pulse, as long as VFB < VREF, LG is off
and UG is on, similar to pure SKIP mode.
18
40μs (MAX)
INDUCTOR
CURRENT
ZERO-CROSSING
DETECTION
0A
FB<REG.POINT
ON-TIME (T ON )
FIGURE 23. ULTRASONIC CURRENT WAVEFORMS
Reference and Linear Regulators (VREF2,
VREF1, and LDO)
The 3.3V reference (VREF2) is accurate to ±1.5% over
temperature, making VREF2 useful as a precision system
reference. VREF2 can supply up to 5mA for external loads.
Bypass VREF2 to GND with a 0.01μF capacitor. Leave open
if there is no load.
The 2V reference (VREF1) is accurate to ±1% over
temperature, also making VREF1 useful as a precision
system reference. Bypass VREF1 to GND with a 0.1μF (min)
capacitor. VREF1 can supply up to 50μA for external loads.
An internal regulator produces a fixed 5V (LDOREF < 0.2V)
or 3.3V (LDOREF > VCC - 1V). In an adjustable mode, the
LDO output can be set from 0.7V to 4.5V. The LDO output
voltage is equal to two times the LDOREF voltage. The LDO
regulator can supply up to 100mA for external loads. Bypass
LDO with a minimum 4.7μF ceramic capacitor. When the
LDOREF < 0.2V and BYP voltage is 5V, the LDO bootstrap-
switch over to an internal 0.7 Ω p-channel MOSFET switch
connects BYP to LDO pin while simultaneously shutting
down the internal linear regulator. These actions bootstrap
the device, powering the loads from the BYP input voltages,
rather than through internal linear regulators from the
battery. Similarly, when the BYP = 3.3V and
LDOREF = VCC, the LDO bootstrap-switch over to an
internal 1.5 Ω P-Channel MOSFET switch connects BYP to
LDO pin while simultaneously shutting down the internal
linear regulator. No switch over action in adjustable mode.
Current-Limit Circuit (ILIM_) with r DS(ON)
Temperature Compensation
The current-limit circuit employs a "valley" current-sensing
algorithm. The ISL8112 uses the on-resistance of the
synchronous rectifier as a current-sensing element. If the
magnitude of the current-sense signal at PH_ is above the
current-limit threshold, the PWM is not allowed to initiate a
new cycle. The actual peak current is greater than the
FN6396.1
August 10, 2010
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| ISL8115 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:High Voltage Synchronous Buck PWM Controller with Integrated Gate Driver and Current Sharing Capability |
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