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| 型号： | ISL8112IRZ-T |
| 厂商： | Intersil |
| 文件页数： | 20/27页 |
| 文件大小： | 0K |
| 描述： | IC REG DL BCK/LINEAR SYNC 32-QFN |
| 标准包装： | 6,000 |
| 拓扑： | 降压（降压）同步（1），线性（LDO）（1） |
| 功能： | 任何功能 |
| 输出数： | 2 |
| 频率 - 开关： | 可调式 |
| 电压/电流 - 输出 1： | 控制器 |
| 电压/电流 - 输出 2： | 0.7 V ~ 4.5 V，200mA |
| 带 LED 驱动器： | 无 |
| 带监控器： | 无 |
| 带序列发生器： | 无 |
| 电源电压： | 4.5 V ~ 25 V |
| 工作温度： | -40°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘 |
| 供应商设备封装： | 32-QFN（5x5） |
| 包装： | 带卷 (TR) |
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ISL8112
Adaptive dead-time circuits monitor the LG_ and UG_
drivers and prevent either FET from turning on until the other
is fully off. This algorithm allows operation without shoot-
through with a wide range of MOSFETs, minimizing delays
and maintaining efficiency. There must be low-resistance,
low-inductance paths from the gate drivers to the MOSFET
gates for the adaptive dead-time circuit to work properly.
Otherwise, the sense circuitry interprets the MOSFET gate
as "off" when there is actually charge left on the gate. Use
very short, wide traces measuring 10 to 20 squares (50 mils
to 100 mils wide if the MOSFET is 1” from the device).
Boost-Supply Capacitor Selection (Buck)
The boost capacitor should be 0.1μF to 4.7μF, depending on
the input and output voltages, external components, and PC
board layout. The boost capacitance should be as large as
possible to prevent it from charging to excessive voltage, but
small enough to adequately charge during the minimum
low-side MOSFET conduction time, which happens at
maximum operating duty cycle (this occurs at minimum input
voltage). The minimum gate to source voltage (V GS(MIN) ) is
determined by:
Fault Protection
The ISL8112 provides overvoltage/undervoltage fault
protection in the buck controllers. Once activated, the
controller continuously monitors the output for undervoltage
and overvoltage fault conditions.
? Out-of-bound Condition
When the output voltage is 5% above the set voltage, the
out-of-bound condition activates. LG turns on until output
reaches within regulation. Once the output is within
regulation, the controller will operate as normal. It is the
"first line of defense" before OVP.
? Overvoltage Protection
When VSEN1 is 11% (16% for VSEN2) above the set
voltage, the overvoltage fault protection activates. This
latches on the synchronous rectifier MOSFET with 100%
duty cycle, rapidly discharging the output capacitor until
the negative current limit is achieved. Once negative
current limit is met, UG is turned on for a minimum on-
time, followed by another LG pulse until negative current
limit. This effectively regulates the discharge current at the
V GS ( MIN ) = PVCC ? ---------------------------------------
C BOOT
C BOOT + C GS
(EQ. 4)
negative current limit in an effort to prevent excessively
large negative currents that cause potentially damaging
negative voltages on the load. Once an overvoltage fault
where:
? PVCC is 5V
? C GS is the gate capacitance of the high-side MOSFET
POR, UVLO, and Internal Digital Soft-Start
Power-on reset (POR) occurs when VIN rises above
approximately 3V. UVLO occurs when PVCC drops below
approximately 4V. The VIN POR reset the LDO control. The
UVLO resets the undervoltage, overvoltage, and thermal-
shutdown fault latches. PVCC undervoltage lockout (UVLO)
circuitry inhibits switching when PVCC is below 4V. LG_ is low
during UVLO. The output voltages begin to ramp up once
PVCC exceeds its 4V UVLO and VREF1 is in regulation. The
internal digital soft-start timer begins to ramp up the
maximum-allowed current limit during start-up. The 1.7ms
ramp occurs in five steps of positive current limit and the step
size is 20%, 40%, 60%, 80% and 100%.
Power-Good Output (PGOOD_)
The PGOOD_ comparator continuously monitors both output
voltages for undervoltage conditions. PGOOD_ is actively
held low in shutdown, standby, and soft-start. PGOOD1
releases and digital soft-start terminates when VSEN1 reach
the error-comparator threshold. PGOOD1 goes low if VOUT1
output turns off or is 10% below its nominal regulation point.
PGOOD1 is a true open-drain output. Likewise, PGOOD2 is
used to monitor VSEN2.
20
condition is set, it can only be reset by toggling SHDN#,
EN_, or cycling PVCC(UVLO).
? Undervoltage Protection
When the output voltage drops below 70% of its regulation
voltage for at least 100μs, the controller sets the fault latch
and begins the discharge mode (see the Shutdown and
Output Discharge section). UVP is ignored for at least
20ms (typical), after start-up or after a rising edge on EN_.
Toggle EN_ or cycle PVCC (UVLO) to clear the
undervoltage fault latch and restart the controller. UVP
only applies to the buck outputs.
? Thermal Protection
The ISL8112 has thermal shutdown to protect the devices
from overheating. Thermal shutdown occurs when the die
temperature exceeds +150°C. All internal circuitry shuts
down during thermal shutdown. The ISL8112 may trigger
thermal shutdown if LDO_ is not bootstrapped from
VSEN_ while applying a high input voltage on VIN and
drawing the maximum current (including short circuit) from
LDO_. Even if LDO_ is bootstrapped from VSEN_,
overloading the LDO_ causes large power dissipation on
the bootstrap switches, which may result in thermal
shutdown. Cycling EN_, EN_LDO, or PVCC(UVLO) ends
the thermal-shutdown state.
FN6396.1
August 10, 2010
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