参数资料
型号: ISL8112IRZ-T
厂商: Intersil
文件页数: 23/27页
文件大小: 0K
描述: IC REG DL BCK/LINEAR SYNC 32-QFN
标准包装: 6,000
拓扑: 降压(降压)同步(1),线性(LDO)(1)
功能: 任何功能
输出数: 2
频率 - 开关: 可调式
电压/电流 - 输出 1: 控制器
电压/电流 - 输出 2: 0.7 V ~ 4.5 V,200mA
带 LED 驱动器:
带监控器:
带序列发生器:
电源电压: 4.5 V ~ 25 V
工作温度: -40°C ~ 100°C
安装类型: 表面贴装
封装/外壳: 32-VFQFN 裸露焊盘
供应商设备封装: 32-QFN(5x5)
包装: 带卷 (TR)
ISL8112
Example: I LOAD(MAX) = 5A, V IN = 12V, V OUT2 = 5V,
f = 200kHz, 35% ripple current or LIR = 0.35:
Output Capacitor Selection
The output filter capacitor must have low enough equivalent
L = ----------------------------------------------------------------- = 8.3 μ H
5V ( 12V – 5V )
12V ? 200kHz ? 0.35 ? 5A
(EQ. 8)
series resistance (ESR) to meet output ripple and
load-transient requirements, yet have high enough ESR to
satisfy stability requirements. The output capacitance must
Find a low-loss inductor having the lowest possible DC
resistance that fits in the allotted dimensions. Ferrite cores
are often the best choice. The core must be large enough
not to saturate at the peak inductor current (IPEAK):
also be high enough to absorb the inductor energy while
transitioning from full-load to no-load conditions without
tripping the overvoltage fault latch. In applications where the
output is subject to large load transients, the output
IPEAK = I LOAD ( MAX ) + [ ( LIR ? 2 ) ? I LOAD ( MAX ) ]
(EQ. 9)
capacitor's size depends on how much ESR is needed to
prevent the output from dipping too low under a load transient.
R SER ≤ ----------------------------------
The inductor ripple current also impacts transient response
performance, especially at low V IN - VSEN_ differences. Low
inductor values allow the inductor current to slew faster,
Ignoring the sag due to finite capacitance:
V DIP
I LOAD ( MAX )
(EQ. 14)
( Δ I LOAD ( MAX ) ) ? L ? K ? ------------------- + t OFF ( MIN ) ? ?
2 ? C OUT ? V OUT K ? -------------------------------- ? - t
R ESR ≤ -----------------------------------------------
V P – P
L IR ? I LOAD ( MAX )
replenishing charge removed from the output filter capacitors
by a sudden load step. The peak amplitude of the output
transient (VSAG) is also a function of the maximum duty
factor, which can be calculated from the on-time and
minimum off-time:
2 ? ? V OUT_ ? ?
? ? V IN ? ?
VSAG = ----------------------------------------------------------------------------------------------------------------------------
? V IN – V OUT ?
? V IN ? OFF ( MIN )
(EQ. 10)
where minimum off-time = 0.35μs (max) and K is from
Table 2.
Determining the Current Limit
The minimum current-limit threshold must be great enough
to support the maximum load current when the current limit
is at the minimum tolerance value. The valley of the inductor
current occurs at ILOAD(MAX) minus half of the ripple
current; therefore:
where V DIP is the maximum-tolerable transient voltage drop.
In non-CPU applications, the output capacitor's size depends
on how much ESR is needed to maintain an acceptable level
of output voltage ripple:
(EQ. 15)
where V P-P is the peak-to-peak output voltage ripple. The
actual capacitance value required relates to the physical size
needed to achieve low ESR, as well as to the chemistry of the
capacitor technology. Thus, the capacitor is usually selected
by ESR and voltage rating rather than by capacitance value
(this is true of tantalum, OS-CON, and other electrolytic-type
capacitors).
When using low-capacity filter capacitors such as polymer
types, capacitor size is usually determined by the capacity
required to prevent VSAG and VSOAR from tripping the
undervoltage and overvoltage fault latches during load
transients in ultrasonic mode.
I LIMIT ( LOW ) > I LOAD ( MAX ) – [ ( LIR ? 2 ) ? I LOAD ( MAX ) ]
(EQ. 11)
For low input-to-output voltage differentials ( V IN / V OUT < 2),
additional output capacitance is required to maintain stability
I PEAK ? L
V SOAR = ------------------------------------------------
2 ? C OUT ? V OUT_
where: I LIMIT(LOW) = minimum current-limit threshold
voltage divided by the r DS(ON) of Q2/Q4.
Use the worst-case maximum value for r DS(ON) from the
MOSFET Q2/Q4 data sheet and add some margin for the
rise in r DS(ON) with temperature. A good general rule is to
allow 0.2% additional resistance for each °C of temperature
rise. Examining the 5A circuit example with a maximum
r DS(ON) = 5m Ω at room temperature. At +125°C reveals the
following:
I LIMIT ( LOW ) = ( 25mV ) ? ( ( 5m Ω × 1.2 ) > 5A – ( 0.35 ? 2 ) 5A )
(EQ. 12)
and good efficiency in ultrasonic mode. The amount of
overshoot due to stored inductor energy can be calculated as:
2
(EQ. 16)
where I PEAK is the peak inductor current.
Input Capacitor Selection
The input capacitors must meet the input-ripple-current
(IRMS) requirement imposed by the switching current. The
ISL8112 dual switching regulator operates at different
frequencies. This interleaves the current pulses drawn by
the two switches and reduces the overlap time where they
add together. The input RMS current is much smaller in
4.17A > 4.12A
(EQ. 13)
comparison than with both SMPSs operating in phase. The
input RMS current varies with load and the input voltage.
4.17A is greater than the valley current of 4.12A, so the circuit
can easily deliver the full-rated 5A using the 30mV nominal
current-limit threshold voltage.
23
The maximum input capacitor RMS current for a single
SMPS is given by:
FN6396.1
August 10, 2010
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