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| 型号： | ISL8112IRZ-T |
| 厂商： | Intersil |
| 文件页数： | 25/27页 |
| 文件大小： | 0K |
| 描述： | IC REG DL BCK/LINEAR SYNC 32-QFN |
| 标准包装： | 6,000 |
| 拓扑： | 降压（降压）同步（1），线性（LDO）（1） |
| 功能： | 任何功能 |
| 输出数： | 2 |
| 频率 - 开关： | 可调式 |
| 电压/电流 - 输出 1： | 控制器 |
| 电压/电流 - 输出 2： | 0.7 V ~ 4.5 V，200mA |
| 带 LED 驱动器： | 无 |
| 带监控器： | 无 |
| 带序列发生器： | 无 |
| 电源电压： | 4.5 V ~ 25 V |
| 工作温度： | -40°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘 |
| 供应商设备封装： | 32-QFN（5x5） |
| 包装： | 带卷 (TR) |
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ISL8112
V IN ( MIN ) = ---------------------------------------------- + 0.1V – 0.1V = 6.65V
1 – ? ------------------------------- ?
V IN ( MIN ) = ----------------------------------------- + 0.1V – 0.1V = 6.04V
1 – ? -------------------------- ?
current. For example, use an MBR0530 (500mA-rated) type
for loads up to 1.5A, a 1N5817 type for loads up to 3A, or a
1N5821 type for loads up to 10A. The rectifier's rated
reverse breakdown voltage must be at least equal to the
maximum input voltage, preferably with a 20% derating
factor.
Applications Information
( 5V + 0.1V )
0.35 μ s ? 1.5
? 2.25 μ s ?
Calculating with h = 1 yields:
( 5V + 0.1V )
0.35 μ s ? 1
? 2.25 μ s ?
(EQ. 23)
(EQ. 24)
( V OUT_ + V DROP )
V IN ( MIN ) = --------------------------------------------------- + V DROP2 – V DROP1
t OFF ( MIN ) ? h
1 – ? ------------------------------------ ?
Dropout Performance
The output voltage-adjust range for continuous-conduction
operation is restricted by the nonadjustable 350ns (max)
minimum off-time one-shot. Use the slower 5V SMPS for the
higher of the two output voltages for best dropout
performance in adjustable feedback mode. The duty-factor
limit must be calculated using worst-case values for on-times
and off-times, when working with low input voltages.
Manufacturing tolerances and internal propagation delays
introduce an error to the FS K-factor. Also, keep in mind that
transient-response performance of buck regulators operated
close to dropout is poor, and bulk output capacitance must
often be added (see Equation 10 on page 23).
The absolute point of dropout occurs when the inductor
current ramps down during the minimum off-time ( Δ I DOWN )
as much as it ramps up during the on-time ( Δ I UP ). The ratio
h = Δ I UP / Δ I DOWN indicates the ability to slew the inductor
current higher in response to increased load, and must
always be greater than 1. As h approaches 1, the absolute
minimum dropout point, the inductor current is less able to
increase during each switching cycle and V SAG greatly
increases unless additional output capacitance is used.
A reasonable minimum value for h is 1.5, but this can be
adjusted up or down to allow trade-offs between V SAG,
output capacitance and minimum operating voltage. For a
given value of h, the minimum operating voltage can be
calculated as:
(EQ. 22)
? K ?
where V DROP1 and V DROP2 are the parasitic voltage drops
in the discharge and charge paths (see “On-Time One-Shot
(FS)” on page 12), t OFF(MIN) is from the “Electrical
Specifications” table on page 4 and K is taken from Table 2.
The absolute minimum input voltage is calculated with h = 1.
Operating frequency must be reduced or h must be
increased and output capacitance added to obtain an
acceptable V SAG if calculated V IN(MIN) is greater than the
required minimum input voltage. Calculate V SAG to be sure
of adequate transient response if operation near dropout is
anticipated.
Dropout Design Example:
ISL8112: With V OUT2 = 5V, fsw = 400kHz, K = 2.25μs,
t OFF(MIN) = 350ns, V DROP1 = V DROP2 = 100mV, and h = 1.5,
the minimum V IN is:
25
Therefore, V IN must be greater than 6.65V. A practical input
voltage with reasonable output capacitance would be 7.5V.
PC Board Layout Guidelines
Careful PC board layout is critical to achieve minimal
switching losses and clean, stable operation. This is
especially true when multiple converters are on the same PC
board where one circuit can affect the other. Refer to the
ISL8112 Evaluation Kit data sheet for a specific layout
example.
Mount all of the power components on the top side of the
board with their ground terminals flush against one another,
if possible. Follow these guidelines for good PC board
layout:
? Isolate the power components on the top side from the
sensitive analog components on the bottom side with a
ground shield. Use a separate PGND plane under the
VSEN1 and VSEN2 sides (called PGND1 and PGND2).
Avoid the introduction of AC currents into the PGND1 and
PGND2 ground planes. Run the power plane ground
currents on the top side only, if possible.
? Use a star ground connection on the power plane to
minimize the crosstalk between VSEN1 and VSEN2.
? Keep the high-current paths short, especially at the
ground terminals. This practice is essential for stable,
jitter-free operation.
? Keep the power traces and load connections short. This
practice is essential for high efficiency. Using thick copper
PC boards (2oz vs. 1oz) can enhance full-load efficiency
by 1% or more. Correctly routing PC board traces must be
approached in terms of fractions of centimeters, where a
single m Ω of excess trace resistance causes a
measurable efficiency penalty.
? PH_ (ISL8112) and GND connections to the synchronous
rectifiers for current limiting must be made using Kelvin-
sense connections to guarantee the current-limit accuracy
with 8-pin SO MOSFETs. This is best done by routing
power to the MOSFETs from outside using the top copper
layer, while connecting PH_ traces inside (underneath) the
MOSFETs.
? When trade-offs in trace lengths must be made, it is
preferable to allow the inductor charging path to be made
longer than the discharge path. For example, it is better to
allow some extra distance between the input capacitors
and the high-side MOSFET than to allow distance
between the inductor and the synchronous rectifier or
between the inductor and the output filter capacitor.
FN6396.1
August 10, 2010
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