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参数资料
| 型号： | ISL8112IRZ-T |
| 厂商： | Intersil |
| 文件页数： | 24/27页 |
| 文件大小： | 0K |
| 描述： | IC REG DL BCK/LINEAR SYNC 32-QFN |
| 标准包装： | 6,000 |
| 拓扑： | 降压（降压）同步（1），线性（LDO）（1） |
| 功能： | 任何功能 |
| 输出数： | 2 |
| 频率 - 开关： | 可调式 |
| 电压/电流 - 输出 1： | 控制器 |
| 电压/电流 - 输出 2： | 0.7 V ~ 4.5 V，200mA |
| 带 LED 驱动器： | 无 |
| 带监控器： | 无 |
| 带序列发生器： | 无 |
| 电源电压： | 4.5 V ~ 25 V |
| 工作温度： | -40°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘 |
| 供应商设备封装： | 32-QFN（5x5） |
| 包装： | 带卷 (TR) |
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ISL8112
? V OUT ( V IN – V OUT_ ) ?
I RMS ≈ I LOAD ? ------------------------------------------------------------ ?
PD ( Q H Switching ) = ( V IN ( MAX ) ) ? ?
2 ? C RSS ? f SW ? I LOAD ?
I GATE
(EQ. 17)
? V IN ?
When V IN = 2 ? V OUT_ ( D = 50% ) , IRMS has maximum
current of I LOAD ? 2 .
The ESR of the input-capacitor is important for determining
capacitor power dissipation. All the power (I RMS2 x ESR)
heats up the capacitor and reduces efficiency. Nontantalum
chemistries (ceramic or OS-CON) are preferred due to their
low ESR and resilience to power-up surge currents. Choose
input capacitors that exhibit less than +10°C temperature
rise at the RMS input current for optimal circuit longevity.
Place the drains of the high-side switches close to each
other to share common input bypass capacitors.
Power MOSFET Selection
Most of the following MOSFET guidelines focus on the
challenge of obtaining high load-current capability (>5A)
when using high-voltage (>20V) AC adapters. Low-current
applications usually require less attention.
Choose a high-side MOSFET (Q1/Q3) that has conduction
adequate r DS(ON) at low battery voltages if it becomes
extraordinarily hot when subjected to V IN(MAX) .
Calculating the power dissipation in NH (Q1/Q3) due to
switching losses is difficult since it must allow for quantifying
factors that influence the turn-on and turn-off times. These
factors include the internal gate resistance, gate charge,
threshold voltage, source inductance, and PC board layout
characteristics. The following switching-loss calculation
provides only a very rough estimate and is no substitute for
bench evaluation, preferably including verification using a
thermocouple mounted on NH (Q1/Q3):
-----------------------------------------------------
? ?
(EQ. 19)
where C RSS is the reverse transfer capacitance of Q H
(Q1/Q3) and I GATE is the peak gate-drive source/sink
current.
For the synchronous rectifier, the worst-case power
dissipation always occurs at maximum battery voltage:
PD ( Q L ) = ? 1 – -------------------------- ? I LOAD ? r DS ( ON )
losses equal to the switching losses at the typical battery
voltage for maximum efficiency. Ensure that the conduction
losses at the minimum input voltage do not exceed the
? V OUT ? 2
? V IN ( MAX ) ?
(EQ. 20)
package thermal limits or violate the overall thermal budget.
Ensure that conduction losses plus switching losses at the
maximum input voltage do not exceed the package ratings
or violate the overall thermal budget.
Choose a synchronous rectifier (Q2/Q4) with the lowest
The absolute worst case for MOSFET power dissipation
occurs under heavy overloads that are greater than
I LOAD(MAX) but are not quite high enough to exceed the
current limit and cause the fault latch to trip. To protect
against this possibility, "overdesign" the circuit to tolerate:
possible r DS(ON) . Ensure the gate is not pulled up by the
high-side switch turning on due to parasitic drain-to-gate
I LOAD = I LIMIT ( HIGH ) + ( ( LIR ) ? 2 ) ? I LOAD ( MAX )
(EQ. 21)
capacitance, causing cross-conduction problems. Switching
losses are not an issue for the synchronous rectifier in the
buck topology since it is a zero-voltage switched device
when using the buck topology.
MOSFET Power Dissipation
Worst-case conduction losses occur at the duty-factor
extremes. For the high-side MOSFET, the worst-case power
dissipation (PD) due to the MOSFET's r DS(ON) occurs at the
minimum battery voltage:
where I LIMIT(HIGH) is the maximum valley current allowed
by the current-limit circuit, including threshold tolerance and
resistance variation.
Rectifier Selection
Current circulates from ground to the junction of both
MOSFETs and the inductor when the high-side switch is off.
As a consequence, the polarity of the switching node is
negative with respect to ground. This voltage is
approximately -0.7V (a diode drop) at both transition edges
PD ( Q H Resistance ) = ? ------------------------ ? ( I LOAD ) ? r DS ( ON )
I L ? r DS ( ON )
? V OUT_ ? 2
? V IN ( MIN ) ?
(EQ. 18)
while both switches are off (dead time). The drop is
when the low-side switch conducts.
Generally, a small high-side MOSFET reduces switching
losses at high input voltage. However, the r DS(ON) required
to stay within package power-dissipation limits often limits
how small the MOSFET can be. The optimum situation
occurs when the switching (AC) losses equal the conduction
( rDS(ON) ) losses.
Switching losses in the high-side MOSFET can become an
insidious heat problem when maximum battery voltage is
applied, due to the squared term in the CV 2 f switching-loss
equation. Reconsider the high-side MOSFET chosen for
24
The rectifier is a clamp across the synchronous rectifier that
catches the negative inductor swing during the dead time
between turning the high-side MOSFET off and the
synchronous rectifier on. The MOSFETs incorporate a
high-speed silicon body diode as an adequate clamp diode if
efficiency is not of primary importance. Place a Schottky
diode in parallel with the body diode to reduce the forward
voltage drop and prevent the Q2/Q4 MOSFET body diodes
from turning on during the dead time. Typically, the external
diode improves the efficiency by 1% to 2%. Use a Schottky
diode with a DC current rating equal to one-third of the load
FN6396.1
August 10, 2010
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