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参数资料
| 型号： | ISL9216IRZ |
| 厂商： | Intersil |
| 文件页数： | 14/33页 |
| 文件大小： | 0K |
| 描述： | IC MULTI-CELL LI-ION PROT 32-QFN |
| 标准包装： | 60 |
| 功能： | 电池监控器 |
| 电池化学： | 锂离子（Li-Ion） |
| 电源电压： | 9.2 V ~ 31 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘 |
| 供应商设备封装： | 32-QFN 裸露焊盘（5x5） |
| 包装： | 管件 |
| 产品目录页面： | 1245 (CN2011-ZH PDF) |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页当前第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页
ISL9216, ISL9217
Registers
TABLE 1. REGISTERS
ADDR
00H
REGISTER
Configuration
READ/WRITE
Read only
7
CU
6
CL
5
Reserved
4
WKUP
3
Reserved
2
Reserved
1
Reserved
0
Reserved
Status
Cascade U
Cascade L
WKUP pin
Status
01H
Operating Status
Read only
Reserved
Reserved
XOT
IOT
LDFAIL
DSC
DOC
COC
(Note 9)
Ext over
temp
Int over
Temp
Load Fail
(VMON)
Short
Circuit
Discharge Charge OC
OC
02H
Cell Balance
Read/Write
CB7ON
CB6ON/
CB5ON
CB4ON
CB3ON
CB2ON
CB1ON
Reserved
WKUPR
Cell balance FET control bits (plus WKUP of ISL9217 in cascade)
03H
Analog Out
Read/Write
UFLG1
UFLG0
Reserved
Reserved
AO3
AO2
AO1
AO0
User Flag 1 User Flag 0
Analog output select bits
04H
FET Control
Read/Write
SLEEP
LDMONEN
Reserved
Reserved
Reserved
Reserved
CFET
DFET
Force
Sleep
(Note 10)
Turn on
VMON
connection
Turn on
Charge
FET
(Note 11)
Turn on
Disharge
FET
(Note 11)
05H
Discharge Set
Read/Write
DENOCD
OCDV1
OCDV0
DENSCD
SCDV1
SCDV0
OCDT1
OCDT0
(Write only if
DISSETEN bit
set)
Turn off
automatic
OCD
Configure Overcurrent
Discharge Threshold
Turn off
automatic
SCD control
Configure Short Circuit
Discharge Threshold
Configure Overcurrent
Discharge Time-out
control
06H
Charge Set
Read/Write
DENOCC
OCCV1
OCCV0
SCLONG
CTDIV
DTDIV
OCCT1
OCCT0
(Write only if
CHSETEN bit
set)
Turn off
automatic
OCC
Configure Overcurrent
Charge Threshold
Long Short-
circuit delay
Divide
charge
time by 32
Divide
discharge
time by 64
Configure Overcurrent
Charge Time-out
control
07H
Feature Set
Read/Write
ATMPOFF
DIS3
TMP3ON
DISXTSD
DISITSD
POR
DISWKUP
WKPOL
(Write only if
Turn off
Disable 3.3V Temp 3.3V
Disable
Disable
Force POR
Disable
Wake-up
FSETEN bit
automatic
reg. (device
keep on
external
internal
WKUP pin
Polarity
set)
external
temp scan
requires
external
thermal
shutdown
thermal
shutdown
3.3V)
08H
Write Enable
Read/Write
FSETEN
CHSETEN
DISSETEN
UFLG3
UFLG2
Reserved
Reserved
Reserved
Enable
Feature
Set writes
Enable
Charge Set
writes
Enable
Discharge
Set writes
User Flag 3 User Flag 2
09H:
Reserved
NA
RESERVED
FFH
NOTES:
7. A “1” written to a control or configuration bit causes the action to be taken. A “1” read from a status bit indicates that the condition exists.
8. “Reserved” indicates that the bit or register is reserved for future expansion. When writing to addresses 2, 3, 4, 6, 7, and 8: write a reserved bit
with the value “0”. Do not write to reserved registers at addresses 09H through FFH. Ignore reserved bits that are returned in a read operation.
9. These status bits are automatically cleared when the register is read. All other status bits are cleared when the condition is cleared.
10. This SLEEP bit is cleared on initial power-up, by the WKUP pin going high (when WKPOL = ”1”) or by the WKUP pin going low (when
WKPOL = ”0”), and by writing a “0” to the location with an I 2 C command.
11. When the automatic responses are enabled, these bits are automatically reset by hardware when an overcurrent or short circuit condition turns
off the FETs. At all other times, an I 2 C write operation controls the output to the respective FET and a read returns the current state of the FET
drive output circuit (though not the actual voltage at the output pin).
12. The shaded registers are not used in the ISL9217 device. Shaded status registers return ‘0’ when read. Shaded “read/write” registers can be read
and written, but they provide no functionality. When writing to the shaded areas in the ISL9217, the locations must be written as “0”.
14
FN6488.1
November 2, 2007
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