参数资料
型号: ISL9216IRZ
厂商: Intersil
文件页数: 27/33页
文件大小: 0K
描述: IC MULTI-CELL LI-ION PROT 32-QFN
标准包装: 60
功能: 电池监控器
电池化学: 锂离子(Li-Ion)
电源电压: 9.2 V ~ 31 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 32-VFQFN 裸露焊盘
供应商设备封装: 32-QFN 裸露焊盘(5x5)
包装: 管件
产品目录页面: 1245 (CN2011-ZH PDF)
ISL9216, ISL9217
S
T
A
R
T
SLAVE
BYTE
REGISTER
ADDRESS
DATA
S
T
O
P
ISL9216 SLAVE BYTE
ISL9217 SLAVE BYTE
0
0
1
1
0
0
1
1
0
0
0
0
0
1
X
X
SDA BUS
0 1 0 1 0 0 x 0
FIGURE 14. DEVICE SLAVE BYTES
A
C
A
C
A
C
K
K
K
ISL9216
HVI2C
ISL9217
ISL9216: x = 0 [SLAVE BYTE = 50H]
RGO
ISL9217: x = 1 [SLAVE BYTE = 52H]
SCL
LEVEL
SCLHV
SCL
FIGURE 12. WRITE SEQUENCE
1010 000x
SHIFT
I 2 C
1010 001x
I 2 C
BLOCK
When receiving data from the master, the value in the data
BLOCK
byte is transferred into the register specified by the address
byte on the falling edge of the clock following the 8th data bit.
LEVEL
SDAOHV
SDAI
After receiving the acknowledge after the data byte, the device
automatically increments the address. So, before sending the
stop bit, the master may send additional data to the device
SDA
SHIFT
LEVEL
SHIFT
SDAIHV
SDAO
without re-sending the slave and address bytes. After writing to
address 0AH, the address “wraps around’ to address 0.
Read Operations
Read operations are initiated in the same manner as write
operations with the host sending the address where the read
is to start (but no data). Then, the host sends an ACK, a
repeated start and the slave byte with the LSB = 1. After the
device acknowledges the slave byte, the device sends out
one bit of data for each master clock. After the slave sends 8
bits to the master, the master sends a NACK (Not
acknowledge) to the device to indicate that the data transfer
is complete, then the master sends a stop bit. See Figure 13.
After sending the eighth data bit to the master, the device
automatically increments its internal address pointer.
Therefore, the master, instead of sending a NACK and the
stop bit, can send additional clocks to read the contents of
the next register - without sending another slave and
address byte.
If the last address read or written is known, the master can
initiate a current address read. In this case, only the slave byte
is sent before data is returned. See Figure 13.
RANDOM READ
FIGURE 15. I 2 C CASCADED INTERFACE
Cascade Operation
When devices are cascaded, the lower device has the I 2 C
slave address of 0101 000x and the upper device has the
address 0101 001x (See Figure 14), but the operation of
cascaded devices is transparent to the microcontroller
master device.
The serial interface between cascaded ISL9216 and
ISL9217 devices has one clock and two data lines. There is
also a high voltage reference for this commication link. See
Figure 15. The interface lines are:
? SCLHV, which is a level shifted clock from the lower
device (ISL9216) to the upper device (ISL9217);
? SDAOHV and SDAO, which send level shifted data out of
the ISL9216 and ISL9217 (respectively); and
? SDAIHV and SDAI, which are level shifted inputs into the
ISL9216 and ISL9217 (respectively).
? HVI2C (ISL9216), which is a reference voltage for the level
shifted interface. This connects to the ISL9217 RGO pin.
CURRENT ADDRESS READ
S
S
S
T
A
R
T
SLAVE
BYTE
REGISTER
ADDRESS
T
A
R
T
SLAVE
BYTE
N
A
C
K
S
T
O
P
T
A
R
T
SLAVE
BYTE
N
A
C
K
S
T
O
P
SDA BUS
0 1 0 1 0 0 0 0
0 1 0 1 0 0 0 1
0 1 0 1 0 0 0 1
A
A
A
A
C
K
C
K
C
K
DATA
C
K
DATA
ISL9208: SLAVE BYTE = 010100xH
FIGURE 13. READ SEQUENCE
27
FN6488.1
November 2, 2007
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