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| 型号： | ISL9216IRZ |
| 厂商： | Intersil |
| 文件页数： | 9/33页 |
| 文件大小： | 0K |
| 描述： | IC MULTI-CELL LI-ION PROT 32-QFN |
| 标准包装： | 60 |
| 功能： | 电池监控器 |
| 电池化学： | 锂离子（Li-Ion） |
| 电源电压： | 9.2 V ~ 31 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘 |
| 供应商设备封装： | 32-QFN 裸露焊盘（5x5） |
| 包装： | 管件 |
| 产品目录页面： | 1245 (CN2011-ZH PDF) |
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ISL9216, ISL9217
Operating Specifications All Specifications Apply to Both the ISL9216 and ISL9217 Separately Over the Recommended Operating
Conditions, Unless Otherwise Specified. (Continued)
DESCRIPTION
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
WAKE-UP/SLEEP SPECIFICATIONS
Device WKUP Pin Voltage Threshold
V WKUP1 WKUP pin rising edge (WKPOL = 1)
3.5
5.0
6.5
V
(WKUP pin active HIGH rising edge)
Device wakes up and sets WKUP flag
HIGH. (ISL9216 only)
Device WKUP Pin Hysteresis
(WKUP pin active HIGH)
V WKUP1H WKUP pin falling edge hysteresis
(WKPOL = 1) sets WKUP flag LOW (does
100
mV
not automatically enter sleep mode)
(ISL9216 only)
Internal Resistor on WKUP
R WKUP
Resistance from WKUP pin to VSS
130
230
330
k Ω
(WKPOL = 1) (ISL9216 only)
Device WKUP Pin Voltage Threshold
(WKUP pin active LOW - Falling Edge)
V WKUP2 WKUP pin falling edge (WKPOL = 0)
Device wakes up and sets WKUP flag
V CELL1 - 2.6 V CELL1 - 2.0 V CELL1 - 1.2
V
HIGH.
Device WKUP Pin Hysteresis
(WKUP pin active LOW)
V WKUP2H WKUP pin rising edge hysteresis
(WKPOL = 0) sets WKUP flag LOW (does
200
mV
not automatically enter sleep mode)
Device Wake-up Delay
t WKUP
Delay after voltage on WKUP pin crosses
20
40
60
ms
the threshold (rising or falling) before
activating the WKUP bit.
FET CONTROL SPECIFICATIONS (For VCELL1, VCELL2, VCELL3 voltages from 2.8V to 4.3V - ISL9216 only)
Control Outputs Response Time
t CO
Bit 0 to start of control signal (DFET)
1.0
μs
(CFET, DFET)
Bit 1 to start of control signal (CFET)
CFET Gate Voltage
DFET Gate Voltage
VCFET
VDFET
No load on CFET
No load on DFET
V CELL3 - 0.5
V CELL3 - 0.5
V CELL3
V CELL3
V
V
FET Turn-on Current (DFET)
FET Turn-on Current (CFET)
I DF(ON)
I CF(ON)
DFET voltage = 0 to VCELL3 - 1.5V
CFET voltage = 0 to VCELL3 - 1.5V
80
80
130
200
400
400
μA
μA
FET Turn-off Current (DFET)
DFET Resistance to VSS
I DF(OFF) DFET voltage = VDFET to 1V
R DF(OFF) VDFET <1V (When turning off the FET)
100
180
11
mA
Ω
SERIAL INTERFACE CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified)
SCL Clock Frequency
f SCL
100
kHz
SCL Falling Edge to SDA Output Data
t AA
From SCL falling crossing V IH (min), until
3.5
μs
Valid
SDA exits the V IL (max) to V IH (min) window.
Time the Bus Must be Free Before Start of
t BUF
SDA crossing V IH (min) during a STOP
4.7
μs
New Transmission
condition to SDA crossing V IH (min) during
the following START condition.
Clock LOW Time
Clock HIGH Time
Start Condition Setup Time
t LOW
t HIGH
t SU:STA
Measured at the V IL (max) crossing.
Measured at the V IH (min) crossing.
SCL rising edge to SDA falling edge. Both
4.7
4.0
4.7
μs
μs
μs
crossing the V IH (min) level.
Start Condition Hold Time
t HD:STA
From SDA falling edge crossing V IL (max) to
4.0
μs
SCL falling edge crossing V IH (min).
Input Data Setup Time
t SU:DAT
From SDA exiting the V IL (max) to V IH (min)
250
ns
window to SCL rising edge crossing
V IL (min).
Input Data Hold Time
t HD:DAT
From SCL rising edge crossing V IH (min) to
300
ns
SDA entering the V IL (max) to V IH (min)
window.
Stop Condition Setup Time
t SU:STO
From SCL rising edge crossing V IH (min) to
4.0
μs
SDA rising edge crossing V IL (max).
9
FN6488.1
November 2, 2007
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