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| 型号： | ISL9216IRZ |
| 厂商： | Intersil |
| 文件页数： | 26/33页 |
| 文件大小： | 0K |
| 描述： | IC MULTI-CELL LI-ION PROT 32-QFN |
| 标准包装： | 60 |
| 功能： | 电池监控器 |
| 电池化学： | 锂离子（Li-Ion） |
| 电源电压： | 9.2 V ~ 31 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘 |
| 供应商设备封装： | 32-QFN 裸露焊盘（5x5） |
| 包装： | 管件 |
| 产品目录页面： | 1245 (CN2011-ZH PDF) |
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ISL9216, ISL9217
User Flags
The ISL9216 and ISL9217 each contain four flags in the
register area that the microcontroller can use for general
purpose indicators. These bits are designated UFLG3, UFLG2,
UFLG1, and UFLG0. The microcontroller can set or reset these
bits by writing into the appropriate register.
The user flag bits are battery backed up, so the contents
remain even after a sleep mode. However, if the mirocontroller
condition is only issued after the transmitting device has
released the bus. See Figure 10.
SCL
SDA
sets the POR bit to force a power on reset, all of the user flags
START
STOP
1
8
9
will also be reset. In addition, if the voltage on cell1 ever drops
below the POR voltage, the contents of the user flags (as well
as all other register values) could be lost.
Serial Interface
INTERFACE CONVENTIONS
The device supports a bi-directional bus oriented protocol.
The protocol defines any device that sends data onto the
bus as a transmitter, and the receiving device as the
receiver. The device controlling the transfer is called the
master and the device being controlled is called the slave.
The master always initiates data transfers, and provides the
clock for both transmit and receive operations. Therefore,
the ISL9216 and ISL9217 devices operate as slaves in all
applications.
When sending or receiving data, the convention is the most
FIGURE 10. I 2 C START AND STOP BITS
ACKNOWLEDGE
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device, either
master or slave, releases the bus after transmitting 8-bits.
During the ninth clock cycle, the receiver pulls the SDA line
LOW to acknowledge that it received the 8-bits of data. See
Figure 11.
SCL FROM
MASTER
DATA OUTPUT
FROM
TRANSMITTER
DATA OUTPUT
FROM RECEIVER
significant bit (MSB) is sent first. So, the first address bit sent
is bit 7.
START
ACKNOWLEDGE
CLOCK AND DATA
Data states on the SDA line can change only while SCL is
LOW. SDA state changes during SCL HIGH are reserved for
indicating start and stop conditions. See Figure 9.
SCL
SDA
FIGURE 11. ACKNOWLEDGE RESPONSE FROM RECEIVER
The device responds with an acknowledge after recognition
of a start condition and the correct slave byte. If a write
operation is selected, the device responds with an
acknowledge after the receipt of each subsequent 8-bits.
The device acknowledges all incoming data and address
bytes, except for the slave byte when the contents do not
match the devices internal pattern.
In the read mode, the device transmits 8-bits of data,
releases the SDA line, then monitors the line for an
DATA
STABLE
DATA
CHANGE
DATA
STABLE
acknowledge. If an acknowledge is detected and no stop
condition is generated by the master, the device will
FIGURE 9. VALID DATA CHANGES ON I 2 C BUS
START CONDITION
All commands are preceded by the start condition, which is a
HIGH to LOW transition of SDA when SCL is HIGH. The
device continuously monitors the SDA and SCL lines for the
start condition and will not respond to any command until
this condition has been met. See Figure 10.
STOP CONDITION
All communications must be terminated by a stop condition,
which is a LOW to HIGH transition of SDA when SCL is
HIGH. The stop condition is also used to place the device
into the Standby power mode after a read sequence. A stop
26
continues to transmit data. The device terminates further
data transmissions if an acknowledge is not detected. The
master must then issue a stop condition to return the device
to Standby mode and place the device into a known state.
WRITE OPERATIONS
For a write operation, the device requires a slave byte and an
address byte. The slave byte specifies which of the devices (in
a cascade configuration) the master is writing to. The address
specifies one of the registers in that device. After receipt of
each byte, the device responds with an acknowledge, and
awaits the next 8-bits from the master. After the acknowledge,
following the transfer of data, the master terminates the transfer
by generating a stop condition. See Figure 12.
FN6488.1
November 2, 2007
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