参数资料
| 型号： | ISLA118P50IRZ |
| 厂商： | Intersil |
| 文件页数： | 11/34页 |
| 文件大小： | 0K |
| 描述： | IC ADC 8BIT SPI/SRL 500M 72QFN |
| 产品培训模块： | Solutions for Test and Measurement Equipment |
| 标准包装： | 1 |
| 系列： | FemtoCharge™ |
| 位数： | 8 |
| 采样率（每秒）： | 500M |
| 数据接口： | 串行，SPI? |
| 转换器数目： | 2 |
| 功率耗散（最大）： | 477mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 72-VFQFN 裸露焊盘 |
| 供应商设备封装： | 72-QFN（10x10） |
| 包装： | 托盘 |
| 输入数目和类型： | 2 个单端，单极；1 个差分，单极 |
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ISLA118P50
19
FN7565.2
July 25, 2011
The criteria above assumes 500MSPS operation; the frequency
bands should be scaled proportionally for lower sample rates.
Note that the effect of excluding energy in the 100kHz band
around of fS/4 exists in every Nyquist zone. This band generalizes
to the form (N*fS/4-50kHz) to (N*fS/4+50kHz), where N is any
odd integer. An input signal that violates these criteria briefly
(approximately 10s), before and after which it meets this
criteria, will not impact system performance.
The algorithm must be in Track Mode for approximately one
second (defined as I2Epost_t in the specification table on
page 7) after power-up before the specifications apply. Once this
requirement has been met, the specifications of the device will
continue to be met while I2E remains in Track Mode, even in the
presence of temperature and supply voltage changes.
Hold Mode refers to the state of the I2E algorithm when the
analog input signal does not meet the requirements specified
above. If the algorithm detects that the signal no longer meets
the criteria, it automatically enters Hold Mode. In Hold Mode, the
I2E circuitry freezes the adjustment values based on the most
recent set of valid input conditions. However, in Hold Mode, the
I2E circuitry will not correct for new changes in interleave
artifacts induced by supply voltage and temperature changes.
The I2E circuitry will remain in Hold Mode until such time as the
analog input signal meets the requirements for Track Mode.
Power Meter
The power meter calculates the average power of the analog
input, and determines if it’s within range to allow operation in
Track Mode. Both AC RMS and total RMS power are calculated,
and there are separate SPI programmable thresholds and
hysteresis values for each.
Notch Filter
A digital filter removes the signal energy in a 100kHz band
around fS/4 before the I2E circuitry uses these samples for
estimating offset, gain, and sample time mismatches (data
samples produced by the A/D are unaffected by this filtering).
This allows the I2E algorithm to continue in Active Run state
while in the presence of a large amount of input energy near the
fS/4 frequency. This filter can be powered down if it’s known that
the signal characteristics won’t violate the restrictions. Powering
down the Notch filter will reduce power consumption by
approximately 70mW.
Nyquist Zones
The I2E circuitry allows the use of any one Nyquist zone without
configuration, but requires the use of only one Nyquist zone.
Inputs that switch dynamically between Nyquist zones will cause
poor performance for the I2E circuitry. For example, I2E will
function properly for a particular application that has
fS = 500MSPS and uses the 1st Nyquist zone (0MHz to 250MHz).
I2E will also function properly for an application that uses
fS = 500MSPS and the 2nd Nyquist zone (250MHz to 500MHz).
I2E will not function properly for an application that uses
fS = 500MSPS, and input frequency bands from 150MHz to
210MHz and 250MHz to 290MHz simultaneously. There is no
need to configure the I2E algorithm to use a particular Nyquist
zone, but no dynamic switching between Nyquist zones is
permitted while I2E is running.
Configurability and Communication
I2E can respond to status queries, be turned on and turned off,
and generally configured via SPI programmable registers.
Configuring of I2E is generally unnecessary unless the
application cannot meet the requirements of Track Mode on or
after power up. Parameters that can be adjusted and read back
include Notch filter threshold and status, Power Meter threshold
and status, and initial values for the offset, gain, and sample
time values to use when I2E starts.
Clock Divider Synchronous Reset
An output clock (CLKOUTP, CLKOUTN) is provided to facilitate
latching of the sampled data. This clock is at half the frequency
of the sample clock, and the absolute phase of the output clocks
for multiple A/Ds is indeterminate. This feature allows the phase
of multiple A/Ds to be synchronized (refer to Figure 38), which
greatly simplifies data capture in systems employing multiple
A/Ds.
The reset signal must be well-timed with respect to the sample
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