参数资料
| 型号： | ISLA118P50IRZ |
| 厂商： | Intersil |
| 文件页数： | 8/34页 |
| 文件大小： | 0K |
| 描述： | IC ADC 8BIT SPI/SRL 500M 72QFN |
| 产品培训模块： | Solutions for Test and Measurement Equipment |
| 标准包装： | 1 |
| 系列： | FemtoCharge™ |
| 位数： | 8 |
| 采样率（每秒）： | 500M |
| 数据接口： | 串行，SPI? |
| 转换器数目： | 2 |
| 功率耗散（最大）： | 477mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 72-VFQFN 裸露焊盘 |
| 供应商设备封装： | 72-QFN（10x10） |
| 包装： | 托盘 |
| 输入数目和类型： | 2 个单端，单极；1 个差分，单极 |
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ISLA118P50
16
FN7565.2
July 25, 2011
(IF) inputs. Two different transformer input schemes are shown in
This dual transformer scheme is used to improve common-mode
rejection, which keeps the common-mode level of the input
matched to VCM. The value of the shunt resistor should be
determined based on the desired load impedance. The
differential input resistance of the ISLA118P50 is 500
Ω.
The SHA design uses a switched capacitor input stage (see
Figure 47), which creates current spikes when the sampling
capacitance is reconnected to the input voltage. This causes a
disturbance at the input which must settle before the next
sampling point. Lower source impedance will result in faster
settling and improved performance. Therefore a 1:1 transformer
and low shunt resistance are recommended for optimal
performance.
A differential amplifier, as shown in Figure 33, can be used in
applications that require DC-coupling. In this configuration, the
amplifier will typically dominate the achievable SNR and
distortion performance.
Clock Input
The clock input circuit is a differential pair (see Figure 48). Driving
these inputs with a high level (up to 1.8VP-P on each input) sine or
square wave will provide the lowest jitter performance. A
transformer with 4:1 impedance ratio will provide increased drive
levels. The clock input is functional with AC-coupled LVDS, LVPECL,
and CML drive levels. To maintain the lowest possible aperture
jitter, it is recommended to have high slew rate at the zero crossing
of the differential clock input signal.
The recommended drive circuit is shown in Figure 34. A duty
range of 40% to 60% is acceptable. The clock can be driven
single-ended, but this will reduce the edge rate and may impact
SNR performance. The clock inputs are internally self-biased to
AVDD/2 to facilitate AC coupling.
Jitter
In a sampled data system, clock jitter directly impacts the
achievable SNR performance. The theoretical relationship
illustrated in Figure 35.
This relationship shows the SNR that would be achieved if clock
jitter were the only non-ideal factor. In reality, achievable SNR is
limited by internal factors such as linearity, aperture jitter and
thermal noise. Internal aperture jitter is the uncertainty in the
sampling instant shown in Figure 3. The internal aperture jitter
combines with the input clock jitter in a root-sum-square fashion,
since they are not statistically correlated, and this determines
the total jitter in the system. The total jitter, combined with other
noise sources, then determines the achievable SNR.
FIGURE 31. TRANSFORMER INPUT FOR GENERAL PURPOSE
APPLICATIONS
ADT1-1WT
0.1F
A/D
VCM
ADT1-1WT
1000pF
FIGURE 32. TRANSMISSION-LINE TRANSFORMER INPUT FOR
HIGH IF APPLICATIONS
ADTL1-12
0.1F
A/D
VCM
ADTL1-12
1000pF
FIGURE 33. DIFFERENTIAL AMPLIFIER INPUT
A/D
VCM
0.1F
0.22F
69.8O
49.9O
100O
69.8O
348O
CM
217O
25O
Ω
FIGURE 34. RECOMMENDED CLOCK DRIVE
TC4-1W
200pF
AVDD
200O
200pF
CLKP
CLKN
1kO
1000pF
Ω
SNR
20 log10
1
2
πf
INtJ
-------------------
=
(EQ. 1)
FIGURE 35. SNR vs CLOCK JITTER
tj = 100ps
tj = 10ps
tj = 1ps
tj = 0.1ps
10 BITS
12 BITS
14 BITS
50
55
60
65
70
75
80
85
90
95
100
1M
10M
100M
1G
SNR
(dB
)
INPUT FREQUENCY (Hz)
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