参数资料
| 型号： | ISLA118P50IRZ |
| 厂商： | Intersil |
| 文件页数： | 6/34页 |
| 文件大小： | 0K |
| 描述： | IC ADC 8BIT SPI/SRL 500M 72QFN |
| 产品培训模块： | Solutions for Test and Measurement Equipment |
| 标准包装： | 1 |
| 系列： | FemtoCharge™ |
| 位数： | 8 |
| 采样率（每秒）： | 500M |
| 数据接口： | 串行，SPI? |
| 转换器数目： | 2 |
| 功率耗散（最大）： | 477mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 72-VFQFN 裸露焊盘 |
| 供应商设备封装： | 72-QFN（10x10） |
| 包装： | 托盘 |
| 输入数目和类型： | 2 个单端，单极；1 个差分，单极 |
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ISLA118P50
14
FN7565.2
July 25, 2011
Theory of Operation
Functional Description
The ISLA118P50 is based upon an 8-bit, 250MSPS A/D converter
core that utilizes a pipelined successive approximation
architecture (Figure 26). The input voltage is captured by a
Sample-Hold Amplifier (SHA) and converted to a unit of charge.
Proprietary charge-domain techniques are used to successively
compare the input to a series of reference charges. Decisions
made during the successive approximation operations determine
the digital code for each input value. The converter pipeline
requires twelve samples to produce a result. Digital error
correction is also applied, resulting in a total latency of 17 clock
cycles. This is evident to the user as a latency between the start of
a conversion and the data being available on the digital outputs.
The device contains two core A/D converters with carefully
matched transfer characteristics. The cores are clocked on
alternate clock edges, resulting in a doubling of the sample rate.
Time–interleaved A/D systems can exhibit non–ideal artifacts in
the frequency domain if the individual core A/D characteristics
are not well matched. Gain, offset and timing skew mismatches
are of primary concern.
The Intersil Interleave Engine (I2E) performs automatic interleave
calibration for the offset, gain, and sample time skew mismatch
between the core A/Ds. The I2E circuitry also adjusts in real-time
for temperature and voltage variations.
Residual gain and sample time skew mismatch result in
fundamental image spurs at fNYQUIST ± fIN. Offset mismatches
create spurs at DC and multiples of fNYQUIST.
Power-On Calibration
As mentioned previously, the cores perform a self-calibration at
start-up. An internal power-on-reset (POR) circuit detects the
supply voltage ramps and initiates the calibration when the
analog and digital supply voltages are above a threshold. The
following conditions must be adhered to for the power-on
calibration to execute successfully:
A frequency-stable conversion clock must be applied to the
CLKP/CLKN pins
DNC pins must not be connected
SDO (pin 66) must be high
RESETN (pin 25) must begin low
SPI communications must not be attempted
A user-initiated reset can subsequently be invoked in the event
that the above conditions cannot be met at power-up.
Pins 3, 4, and SDO require an external 4.7k
Ω pull-up to OVDD. If
these pins are pulled low externally during power-up, calibration
will not be executed properly.
After the power supply has stabilized the internal POR releases
RESETN and an internal pull-up pulls it high, which starts the
calibration sequence. If a subsequent user-initiated reset is
desired, the RESETN pin should be connected to an open-drain
driver with a drive strength in its high impedance state of less
than 0.5mA.
The calibration sequence is initiated on the rising edge of
RESETN, as shown in Figure 27. The over-range output (OR) is set
high once RESETN is pulled low, and remains in that state until
calibration is complete. The OR output returns to normal
operation at that time, so it is important that the analog input be
within the converter’s full-scale range to observe the transition. If
the input is in an over-range condition the OR pin will stay high,
and it will not be possible to detect the end of the calibration
cycle.
DIGITAL
ERROR
CORRECTION
SHA
1.25V
INP
INN
CLOCK
GENERATION
2.5-BIT
FLASH
6-STAGE
1.5-BIT/STAGE
3-STAGE
1-BIT/STAGE
3-BIT
FLASH
LVDS/LVCMOS
OUTPUTS
+
–
FIGURE 26. A/D CORE BLOCK DIAGRAM
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