参数资料
| 型号： | ISLA214S50IR1Z |
| 厂商： | Intersil |
| 文件页数： | 10/41页 |
| 文件大小： | 0K |
| 描述： | IC ADC |
| 标准包装： | 1 |
| 系列： | * |
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ISLA214S50
18
FN7973.2
April 25, 2013
used in certain AC applications with minimal performance
degradation. Contact the factory for more information.
When an over range occurs, the data sample output bits are held
at full scale (all 0’s or all 1’s), thus allowing the detection of this
condition in the receiver device.
Clock Input
The clock input circuit is a differential pair (see Figure 49).
Driving these inputs with a high level (up to 1.8VP-P on each
input) sine or square wave will provide the lowest jitter
performance. A transformer with 4:1 impedance ratio will
provide increased drive levels. The clock input is functional with
AC-coupled LVDS, LVPECL, and CML drive levels. To maintain the
lowest possible aperture jitter, it is recommended to have high
slew rate at the zero crossing of the differential clock input
signal.
The recommended drive circuit is shown in Figure 37. A duty
range of 40% to 60% is acceptable. The clock can be driven
single-ended, but this will reduce the edge rate and may impact
SNR performance. The clock inputs are internally self-biased to
AVDD/2 through a Thevenin equivalent of 10kΩ to facilitate AC
coupling.
A selectable 2x frequency divider is provided in series with the
clock input. The divider can be used in the 2x mode with a
sample clock equal to twice the desired sample rate. Use of the
2x frequency divider enables the use of the Phase Slip feature,
which enables the system to be able to select the phase of the
divide by 2 that causes the ADC to sample the analog input.
The clock divider can also be controlled through the SPI port,
which overrides the CLKDIV pin setting. See “SPI Physical
Interface” on page 26. A delay-locked loop (DLL) generates
internal clock signals for various stages within the charge
pipeline. If the frequency of the input clock changes, the DLL may
take up to 52μs to regain lock at 500MSPS. The lock time is
inversely proportional to the sample rate.
The DLL has two ranges of operation, slow and fast. The slow
range can be used for ADC sample rates between 80MSPS and
200MSPS, while the default fast range can be used from
160MSPS to the maximum specified sample rate. The lane data
rate is related to the ADC core sample rate by a relationship that
is defined by the JESD204 transmitter configuration, and has
additional frequency constraints; see“JESD204 Transmitter” on
page 21 for additional details.
Jitter
In a sampled data system, clock jitter directly impacts the
achievable SNR performance. The theoretical relationship
illustrated in Figure 38.
This relationship shows the SNR that would be achieved if clock
jitter were the only non-ideal factor. In reality, achievable SNR is
limited by internal factors such as linearity, aperture jitter and
thermal noise as well. Internal aperture jitter is the uncertainty in
the sampling instant. The internal aperture jitter combines with
the input clock jitter in a root-sum-square fashion, since they are
not statistically correlated, and this determines the total jitter in
the system. The total jitter, combined with other noise sources,
then determines the achievable SNR.
Voltage Reference
A temperature compensated internal voltage reference provides
the reference charges used in the successive approximation
operations. The full-scale range of each ADC is proportional to
the reference voltage. The nominal value of the voltage reference
is 1.25V.
Digital Outputs
The digital outputs are in CML format, and feature analog and
digital characteristics compliant with the JESD204 standard
requirements.
Power Dissipation
The power dissipated by the device is dependent on the ADC
sample rate and the number of active lanes in the link. There is a
fixed bias current drawn from the analog supply for the ADC,
along with a fixed bias current drawn from the digital supply for
each active lane. The remaining power dissipation is linearly
related to the sample rate.
TABLE 1. CLKDIV PIN SETTINGS
CLKDIV PIN
DIVIDE RATIO
AVSS
2
Float
1
AVDD
Not Allowed
FIGURE 37. RECOMMENDED CLOCK DRIVE
TC4-19G2+
1000pF
CLKP
CLKN
0.01F
200
1000pF
SNR
20 log
10
1
2
πf
IN tJ
--------------------
=
(EQ. 1)
FIGURE 38. SNR vs CLOCK JITTER
tj = 100ps
tj = 10ps
tj = 1ps
tj = 0.1ps
10 BITS
12 BITS
14 BITS
50
55
60
65
70
75
80
85
90
95
100
1M
10M
100M
1G
SNR
(dB)
INPUT FREQUENCY (Hz)
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