参数资料
| 型号： | ISLA214S50IR1Z |
| 厂商： | Intersil |
| 文件页数： | 15/41页 |
| 文件大小： | 0K |
| 描述： | IC ADC |
| 标准包装： | 1 |
| 系列： | * |
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ISLA214S50
22
FN7973.2
April 25, 2013
To maximize flexibility at the system level, two transport layer
packing modes are supported: simple and efficient. These two
modes allow the system designer flexibility to trade off between
the number of lanes to support a given throughput, the data rate
of these lanes, and the complexity of the receiver. This translates
directly into providing system level trade-offs between cost,
power, and resource usage of the receiver and complexity of the
solution.
Simple mode packs informationless bits onto each ADC sample
to form full 16-bit data. In simple mode packing, the frame clock
and ADC sample clock are the same frequency, easing frequency
scaling requirements at the system level, but decreasing the
payload efficiency of the lanes. Decreased payload efficiency of
the lanes increases the lane data rate required to support a given
throughput, and may require additional lanes to support a given
configuration. The degree of payload efficiency loss is dependent
on the ADC resolution.
Efficient mode packs sequential ADC samples into a contiguous
block of an integer number of octets, and then slices the block
into the octets for transport. This mode always achieves the
theoretical maximum payload of the lanes (80%) regardless of
the resolution of the ADC and the number of lanes used. This
mode provides the minimum number of lanes at the minimum
data rate that is theoretically possible given the 8b/10b
encoding used in JESD204 systems. In efficient packing mode,
frame clock and the ADC sample clock have an M/N relationship,
where M and N are small integers and vary depending on the
ADC resolution and number of lanes selected. Efficient mode
packing may require additional frequency scaling elements
(internal FPGA PLLs or discrete frequency scaling devices) to
generate the frame clock for the receiving device.
The default configuration for this device is efficient packing mode.
Reconfiguration into the simple packing mode is accomplished by
programming the JESD204 parameters via the SPI bus. See
Table 5 for the full list of parameters values for each mode and
product. Via SPI, the JESD204 transmitter is highly configurable,
supporting efficient to simple mode packing reconfiguration as
well as "downgrading" a given product's JESD204 interface. For
example, reconfiguring a 3-lane product into 2 lanes (with each
running faster than with 3 lanes), or reducing the resolution of the
ADC(s) to slow down the lane data rate in systems where the full
ADC resolution is not required, are supported. Please contact the
factory for a full list of downgradeable configurations that are
supported.
Signal integrity plots, including data eye, BER bathtub curves,
and edge histogram plots versus lane data rate can be found in
the typical operating curves section.
Initial Lane Alignment
The link initialization process is started by asserting the SYNC~
signal to the ADC device. This assertion causes the JESD204
transmitter to generate comma characters, which are used by
the receiver to accomplish code group synchronization (bit and
octet alignment, respectively). Once code group synchronization
is detected in the receiver, it de-asserts the SYNC~ signal,
causing the JESD204 transmitter to generate the initial lane
alignment sequence (ILA). The ILA is comprised of 4
multi-frames of data in a standard format, with the length of
each multi-frame determined by the K parameter as
programmed into the SPI JESD204 parameter table. The ILA
includes standard control character markers that can be used to
perform channel bonding in the receiving device if desired. The
2nd multi-frame includes the full JESD204 parameter data,
allowing the receiver to auto-detect the lane configuration if
desired.
After completion of the ILA the JESD204 transmitter begins
transmitting ADC sample data. Continuous link and lane
alignment monitoring is accomplished via an octet substitution
scheme. The last octet in each frame, if identical to the last octet
in the previous frame, is replaced with a specific control
character. If both sides of the link support lane synchronization,
the last octet in each multi-frame, if identical to the last octet in
the previous frame, is replaced with a different specific control
character. A more complete description of the link initialization
sequence, including finite state machine implementation, can be
found in the JESD204 rev A standard.
LANE DATA RATE
The lane data rate for this product family is constrained to be
greater than or equal to 1Gbps and less than or equal to
3.125Gbps for guaranteed operation, so as to be consistent with
the lane data rate limit of 3.125Gbps set by the JESD204 rev A
standard. The lane data rate can typically exceed 4.2Gbps for this
product family.
SCRAMBLER
The bypassable scrambler is compliant with the scrambler
defined in the JESD204 rev A standard.
This implementation seeds the scrambler with the initial lane
alignment sequence, such that the first two octets following the
sequence can be properly descrambled if the receiver also
passes the lane alignment sequence through its descrambler.
Even if the receiver does not implement this detail, the 3rd and
subsequent octets can be descrambled to yield ADC data due to
the self-synchronizing nature of the scrambler used.
MULTI-CHIP TIME ALIGNMENT
The JESD204 standard (in various revisions) provides the
capability to time align multiple JESD204 ADC devices to a single
logic device (FPGA or ASIC). This feature is critical in many
applications that cannot tolerate the variable latency of the
JESD204 link, and that must process pipeline depth correct data
from more than one ADC device.
Time alignment of multiple devices provides the capability to
align samples from multiple JESD204 ADC devices in the system
in a pipeline-depth correct manner, thus enabling the system to
analyze the ADC data from multiple devices while eliminating the
variable latency of the JESD204 link as a concern. This capability
enables configurations of JESD204 ADCs as IQ, interleave,
and/or simultaneously-sampled converters.
This ADC family uses the asserted to de-asserted SYNC~
transition as the absolute time event with which to generate a
known sequence of characters at the JESD204 transmitter of
equal pipeline depth between all ADC devices in the system to be
time aligned. This is consistent with the JESD204 rev B
subclass 2 device definition.
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