参数资料
| 型号： | ISLA214S50IR1Z |
| 厂商： | Intersil |
| 文件页数： | 14/41页 |
| 文件大小： | 0K |
| 描述： | IC ADC |
| 标准包装： | 1 |
| 系列： | * |
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ISLA214S50
21
FN7973.2
April 25, 2013
Clock Divider Synchronous Reset
The function of clock divider synchronous reset is available as a
SPI-programmable overloaded function on the SYNCP and
SYNCN pins. Given that the clock divider reset and SYNC features
have the same electrical and timing requirements, this
overloading allows the system to generate only a single well
timed signal with respect to the ADC sample clock and select the
ADC’s interpretation of the signal as a SPI-programmable option
(see SPI register 0x77 description for more information). By
default the SYNCP and SYNCN pins will function as the JESD204
SYNC~.
The use of clock divider reset function is a requirement in a
system that uses the ISLA214S50, ISLA214S35, or CLKDIV = 2,
and also requires time alignment or deterministic latency of
multiple devices. Please contact the factory for more details
about this feature and its usage.
Soft Reset
Soft reset is a function intended to be used when the power on
reset is to be re-run. An application may decide to issue a soft
calibration command after significant temperature change or
after a change in the sample rate frequency to optimize
performance under the new condition.
Soft reset is issued by writing the Soft Reset bit at SPI address
0x00. Soft reset is a self-resetting bit in that will automatically
return to 0 once the power on calibration has completed.
JESD204 Transmitter
Overview
The conversion data is presented by a JESD204B-compliant
SERDES interface. The SERDES lane data rate supports typical
speeds up to 4.375Gbps, exceeding the 3.125Gbps maximum
specified by the JESD204 rev A standard. Two packing modes are
supported: Efficient and Simple. A SYNC input is included, which
is used for lane initialization as well as time alignment of
multiple converter devices. AC coupling of the SERDES lane(s) on
the board is required. A block diagram of this SERDES
transmitter is shown in Figure 41.
For more information about the standardized characteristics and
features of a JESD204 interface, please see JESD204 rev A and rev
B standards. For application design support, including evaluation kit
schematics and layout, reference FPGA project(s), and simulation
models for functionality and signal integrity, please contact the
factory and/or view application notes on the Intersil website.
FIGURE 41. SERDES TRANSMITTER BLOCK DIAGRAM
Sample
Clock
Sample Data
Transport
Layer
Scrambler
1+x
14+x15
Encoder
8/10
Link Layer
SYNC
PLL
Multiply
- Code group Synchronization
- Alignment Characters
- Initial Lane Synchronization
- Etc
SER
Logic
Lane 0
Link Layer
SERDES Block
Lane 1
Link Layer
Lane 2
Sample Data
Analog
Input
Analog
Input
Clock
Management
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