参数资料
| 型号： | ISLA214S50IR1Z |
| 厂商： | Intersil |
| 文件页数： | 16/41页 |
| 文件大小： | 0K |
| 描述： | IC ADC |
| 标准包装： | 1 |
| 系列： | * |
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ISLA214S50
23
FN7973.2
April 25, 2013
Test Patterns
The complexity of the JESD204 interface merits much more test
pattern capability than less complex parallel interfaces. This
device family consequently supports a much wider range of test
patterns than previous ADC families.
Supported test patterns include both transport and link layer
patterns. Transport layer patterns are passed through the
transport layer of the JESD204 transmitter, following the same
sequence of being packed and sliced into octets as the ADC
sample data. Link layer test patterns bypass the transport layer
and are injected directly into the 8b/10b encoder, serialized, and
sent out of the physical media. Test pattern generation is
controlled through SPI register 0xC0.
Link layer PRBS patterns are standard PRBS patterns that can be
used with built-in standard PRBS checkers in, for example, FPGA
SERDES-capable pins.
All transport layer test patterns re-initialize their phase when the
SYNC~ de-assertion occurs; consequently, a system that provides
a well-timed SYNC~ signal with respect to the ADC sample clock
can expect transport layer test patterns to have consistent phase
with respect to that de-assertion, which can be a significant aid
when debugging the system.
TABLE 4. JESD204 CONFIGURATIONS AND CLOCK FREQUENCIES
PRODUCT
DESCRIPTION
PACKING
MODE
NUMBER
OF LANES
ADC SAMPLE CLOCK
RANGE (MHz) (Note 16)
LANE DATA RATE MULTIPLIER FROM ADC SAMPLE
CLOCK RATE
LANE DATA RATE
(GBPS) (Note 16)
ISLA214S50
500MSPS,
14-bit
Efficient
3
200 to 500
(14-bits)*(1 ADC channel)*(10/8 encoder
overhead)/(3 lanes) = (140/24) = 5.8333
1.16667 to
2.916675
ISLA214S35
350MSPS,
14-bit
Efficient
2
175 to 350
(14-bits)*(1 ADC channel)*(10/8 encoder
overhead)/(2 lanes) = (140/16) = 8.75
1.53125 to
3.0625
Simple
2
175 to 310
(14-bits+2-bit tail)*(1 ADC channel)*(10/8
encoder overhead)/(2 lanes) = (160/16) = 10
1.75 to 3.1
NOTE:
16. Maximum sample clock range calculated using the smaller of the maximum ADC core sample rate and the 3.125 Gbps maximum lane data rate
dictated in the JESD204 rev A standard. Typically the maximum lane data rate achievable on these products far exceeds 3.125Gbps.
TABLE 5. JESD204 PARAMETERS
PRODUCT
PACKING
MODE
NUMBER
OF
LANES
JESD204
PARAMETER ENCODED
ISLA214S50 Efficient
3
CF = 0
0
CS = 0
0
C0S0[13:6] C0S0[5:0]
C0S1[11:4] C0S1[3:0]
C0S2[9:2]
C0S2[1:0]
C0S3[7:0]
F = 7
6
C0S1[13:12]
C0S2[13:10]
C0S3[13:8]
HD = 0
0
L = 3
2
C0S4[13:6] C0S4[5:0]
C0S5[11:4] C0S5[3:0]
C0S6[9:2]
C0S6[1:0]
C0S7[7:0]
M = 1
0
C0S5[13:12]
C0S6[13:10]
C0S7[13:8]
N = 14
13
N' = 14
13
C0S8[13:6] C0S8[5:0]
C0S9[11:4] C0S9[3:0]
C0S10[9:2] C0S10[1:0] C0S11[7:0]
S = 12
11
C0S9[13:12]
C0S10[13:10]
C0S11[13:8]
K >= 3
>= 2
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