参数资料
| 型号： | ISLA224S20IR1Z |
| 厂商： | Intersil |
| 文件页数： | 13/38页 |
| 文件大小： | 0K |
| 描述： | IC ADC |
| 标准包装： | 1 |
| 系列： | * |
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ISLA224S
20
FN7911.2
April 25, 2013
pin must be first set to Normal before the SPI port will be enabled.
Therefore, before the SPI port can be used to override the NAPSLP
pin setting, the ADC must have been put into Normal mode at
least once using the NAPSLP pin. Further details on the SPI port
are contained in “Serial Peripheral Interface” on page 25.
Data Format
Output data can be presented in three formats: two’s
complement(default), Gray code and offset binary. The data
format can be controlled through the SPI port by writing to
address 0x73. Details on this are contained in “Serial Peripheral
Offset binary coding maps the most negative input voltage to
code 0x000 (all zeros) and the most positive input to 0xFFF (all
ones). Two’s complement coding simply complements the MSB
of the offset binary representation.
When calculating Gray code the MSB is unchanged. The remaining
bits are computed as the XOR of the current bit position and the
next most significant bit. Figure 48 shows this operation.
Converting back to offset binary from Gray code must be done
recursively, using the result of each bit for the next lower bit as
shown in Figure 49.
Mapping of the input voltage to the various data formats is
shown in Table 3..
Clock Divider Synchronous Reset
The function of clock divider synchronous reset is available as a
SPI-programmable overloaded function on the SYNCP and SYNCN
pins. Given that the clock divider reset and SYNC features have the
same electrical and timing requirements, this overloading allows
the system to generate only a single well timed signal with respect
to the ADC sample clock and select the ADC’s interpretation of the
signal as a SPI-programmable option (see SPI register 0x77
description for more information). By default the SYNCP and
SYNCN pins will function as the JESD204 SYNC~.
The use of clock divider reset function is a requirement in a
system that uses the ISLA214S50, ISLA214S35, or CLKDIV = 2
or 4 and also requires time alignment or deterministic latency of
multiple devices. Please contact the factory for more details
about this feature and its usage.
Soft Reset
Soft reset is a function intended to be used when the power on
reset is to be re-run. An application may decide to issue a soft
calibration command after significant temperature change or
after a change in the sample rate frequency to optimize
performance under the new condition.
Soft reset is issued by writing the Soft Reset bit at SPI address
0x00. Soft reset is a self-resetting bit in that will automatically
return to 0 once the power on calibration has completed.
JESD204 Transmitter
Overview
The conversion data is presented by a JESD204B-compliant
SERDES interface. The SERDES lane data rate supports typical
speeds up to 4.375Gbps, exceeding the 3.125Gbps maximum
specified by the JESD204 rev A standard. Two packing modes are
supported: Efficient and Simple. A SYNC input is included, which
is used for lane initialization as well as time alignment of
multiple converter devices. AC coupling of the SERDES lane(s) on
the board is required. A block diagram of this SERDES
transmitter is shown in Figure 50.
For more information about the standardized characteristics and
features of a JESD204 interface, please see JESD204 rev A and rev
B standards. For application design support, including evaluation kit
schematics and layout, reference FPGA project(s), and simulation
models for functionality and signal integrity, please contact the
factory and/or view application notes on the Intersil website.
FIGURE 48. BINARY TO GRAY CODE CONVERSION
12
13
11
0
1
BINARY
12
13
11
0
GRAY CODE
1
FIGURE 49. GRAY CODE TO BINARY CONVERSION
12
13
11
0
1
BINARY
12
13
11
0
GRAY CODE
1
TABLE 3. INPUT VOLTAGE TO OUTPUT CODE MAPPING
INPUT
VOLTAGE
OFFSET BINARY
TWO’S
COMPLEMENT
GRAY CODE
–Full Scale 00 0000 0000 0000 10 0000 0000 0000 00 0000 0000 0000
–Full Scale
+ 1LSB
00 0000 0000 0001 10 0000 0000 0001 00 0000 0000 0001
Mid–Scale 10 0000 0000 0000 00 0000 0000 0000 11 0000 0000 0000
+Full Scale
– 1LSB
11 1111 1111 1110 01 1111 1111 1110 10 0000 0000 0001
+Full Scale 11 1111 1111 1111 01 1111 1111 1111 10 0000 0000 0000
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