ISLA224S20IR1Z (Intersil) PDF资料下载 Datasheet(21/38 页)

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参数资料

型号：	ISLA224S20IR1Z
厂商：	Intersil
文件页数：	21/38页
文件大小：	0K
描述：	IC ADC
标准包装：	1
系列：	*

ISLA224S

FN7911.2

April 25, 2013

ADDRESS 0X73: OUTPUT_MODE_A

The output_mode_A register controls the logical coding of the

sample data. Data can be coded in three possible formats: two’s

complement(default), Gray code or offset binary. See Table 12.

This register is not changed by a Soft Reset.

ADDRESS 0X74: OUTPUT_MODE_B

Bit 6 DLL Range

This bit sets the DLL operating range to fast (default) or slow.

Internal clock signals are generated by a delay-locked loop (DLL),

which has a finite operating range. Table 13 shows the allowable

sample rate ranges for the slow and fast settings.

ADDRESS 0X77: SYNC_FUNCTION

BIT 0 CLKDIVRST

This bit controls the functionality of the SYNCP, SYNCN pins on

this device. By default, this bit equals ‘0’, which means that the

functionality of the SYNCP, SYNCN pins is the JESD204 SYNC.

Setting this bit equal to ‘1’ modifies the functionality of the

SYNCP, SYNCN pins to be clkdivrst, which is a synchronous

divider reset on all internal dividers in the device. Usage of this

clkdivrst functionality is required to support multi-chip time

alignment and deterministic latency for devices that use

interleaved product configurations (ISLA214S50 and

ISLA214S35), and for any other product configuration that uses

clkdiv > 1. In both states, the setup and hold times with respect

to the sample clock remain the same. Contact the factory for

more details.

ADDRESS 0XB6: CALIBRATION STATUS

The LSB at address 0xB6 can be read to determine calibration

status. The bit is ‘0’ during calibration and goes to a logic ‘1’

when calibration is complete.This register is unique in that it can

be read after POR at calibration, unlike the other registers on

chip, which can’t be read until calibration is complete.

DEVICE TEST

The device can produce preset or user defined patterns on the

digital outputs to facilitate in-situ testing. A user can pick from

preset built-in patterns by writing to the output test mode field

[7:4] at 0xC0 or user defined patterns by writing to the user test

mode field [2:0] at 0xC0. The user defined patterns should be

loaded at address space 0xC1 through 0xD0, see the “SPI

Memory Map” on page 31 for more detail. The test mode is

enabled asynchronously to the sample clock, therefore several

sample clock cycles may elapse before the data is present on the

output bus.

ADDRESS 0XC0: TEST_IO

Bits 7:4 Output Test Mode

These bits set the test mode according to the description in “SPI

Memory Map” on page 31.

Bits 2:0 User Test Mode

The three LSBs in this register determine the test pattern in

combination with registers 0xC1 through 0xD0. Refer to the “SPI

Memory Map” on page 31.

ADDRESS 0XC1: USER_PATT1_LSB

ADDRESS 0XC2: USER_PATT1_MSB