参数资料
| 型号： | ISLA224S20IR1Z |
| 厂商： | Intersil |
| 文件页数： | 25/38页 |
| 文件大小： | 0K |
| 描述： | IC ADC |
| 标准包装： | 1 |
| 系列： | * |
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ISLA224S
31
FN7911.2
April 25, 2013
SPI Memory Map
ADDR.
(Hex)
PARAMETER NAME
BIT 7
(MSB)
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
(LSB)
DEF. VALUE
(HEX)
SPI
Co
nfig
/Con
tr
ol
00
port_config
SDO Active LSB First Soft Reset
Mirror
(bit5)
Mirror
(bit6)
Mirror
(bit7)
00h
01
Reserved
02
burst_end
Burst end address [7:0]
00h
03-07
Reserved
DU
TIn
fo
08
chip_id
Chip ID #
Read only
09
chip_version
Chip Version #
Read only
0A-0F
Reserved
De
vi
ce
Co
nfig/Co
ntrol
10-1F
Reserved
20
offset_coarse_coreA
Coarse Offset
cal. value
21
offset_fine_coreA
Fine Offset
cal. value
22
gain_coarse_coreA
Reserved
Coarse Gain
cal. value
23
gain_medium_coreA
Medium Gain
cal. value
24
gain_fine_coreA
Fine Gain
cal. value
25
modes_coreA
Reserved
Power Down Mode coreA [2:0]
000 = Pin Control
001 = Normal Operation
010 = Nap
100 = Sleep
Other codes = Reserved
00h
NOT reset by
Soft Reset
26
offset_coarse_coreB
Coarse Offset
cal. value
27
offset_fine_coreB
Fine Offset
cal. value
28
gain_coarse_coreB
Reserved
Coarse Gain
cal. value
29
gain_medium_coreB
Medium Gain
cal. value
2A
gain_fine_coreB
Fine Gain
cal. value
2B
modes_coreB
Reserved
Power Down Mode coreB [2:0]
000 = Pin Control
001 = Normal Operation
010 = Nap
100 = Sleep
Other codes = Reserved
00h
NOT reset by
Soft Reset
2C-6F
Reserved
70
skew_diff
Differential Skew
80h
71
phase_slip
Reserved
Next Clock
Edge
00h
72
clock_divide
Clock Divide [2:0]
000 = Pin Control
001 = divide by 1
010 = divide by 2
100 = divide by 4
Other codes = Reserved
00h
NOT reset by
Soft Reset
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