参数资料
| 型号： | ISLA224S20IR1Z |
| 厂商： | Intersil |
| 文件页数： | 20/38页 |
| 文件大小： | 0K |
| 描述： | IC ADC |
| 标准包装： | 1 |
| 系列： | * |
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ISLA224S
27
FN7911.2
April 25, 2013
are 8-bit. Multiple Coarse Gain Bits can be set for a total
adjustment range of ±4.2%. (‘0011’
-4.2% and ‘1100’ +4.2%)
It is recommended to use one of the coarse gain settings (-4.2%,
-2.8%, -1.4%, 0, 1.4%, 2.8%, 4.2%) and fine-tune the gain using the
registers at 0x0023 and 0x24.
The default value of each register will be the result of the
self-calibration after initial power-up. If a register is to be
incremented or decremented, the user should first read the
register value then write the incremented or decremented value
back to the same register. Bit 0 in register 0xFE must be set high
to enable updates written to 0x23 and 0x24 to be used by the
ADC.(See description for 0xFE).
ADDRESS 0X25: MODES
Two distinct reduced power modes can be selected. By default,
the tri-level NAPSLP pin can select normal operation, nap or
sleep modes (refer to"Nap/Sleep" on page 19). This functionality
can be overridden and controlled through the SPI. However, if
the ADC is powered-on with the NAPSLP pin in either Nap or
Sleep modes, the pin must first be set to Normal before the SPI
port will be enabled. Therefore, before the SPI port can be used
to override the NAPSLP pin setting, the ADC must have been put
into Normal mode at least once using the NAPSLP pin. This
register is not changed by a Soft Reset.
ADDRESS 0X26: OFFSET_COARSE_COREB
ADDRESS 0X27: OFFSET_FINE_COREB
The input offset of ADC coreB can be adjusted in fine and coarse
steps in the same way that offset for coreA can be adjusted. Both
adjustments are made via an 8-bit word as detailed in Table 7.
The data format is two’s complement.
The default value of each register will be the result of the
self-calibration after initial power-up. If a register is to be
incremented or decremented, the user should first read the
register value then write the incremented or decremented value
back to the same register. Bit 0 in register 0xFE must be set high
to enable updates written to 0x26 and 0x27 to be used by the
ADC.(See description for 0xFE)
ADDRESS 0X28: GAIN_COARSE_COREB
ADDRESS 0X29: GAIN_MEDIUM_COREB
ADDRESS 0X2A: GAIN_FINE_COREB
Gain of ADC coreB can be adjusted in coarse, medium and fine
steps in the same way that coreA can be adjusted. Coarse gain is a
4-bit adjustment while medium and fine are 8-bit. Multiple Coarse
Gain Bits can be set for a total adjustment range of ±4.2%. Bit 0 in
register 0xFE must be set high to enable updates written to 0x29
and 0x2A to be used by the ADC.(See description for 0xFE)
Global Device Configuration/Control
ADDRESS 0X71: PHASE_SLIP
When using the clock_divide feature, the sample clock edge that
the ADC uses to sample the analog input signal can be one of
several different edges on the incoming higher frequency sample
clock. For example, in clock_divide = 2 mode, every other
incoming sample clock edge gets used by the ADC to sample the
analog input. The phase_slip feature allows the system to control
which edge of the incoming sample clock signals gets used to
cause the sampling event, by “slipping” the sampling event by
one input clock period each time phase_slip is asserted.
The clkdivrst feature can work in conjunction with phase_slip.
After well-timed assertion of the clkdivrst signal (via overloading
on the SYNC inputs), the sampling edge position with respect to
the incoming clock rate will have been reset, allowing the system
to “slip” whatever desired number of incoming clock periods
from a known state.
ADDRESS 0X72: CLOCK_DIVIDE
The ADC has a selectable clock divider that can be set to divide
by two or one (no division). By default, the tri-level CLKDIV pin
selects the divisor This functionality can be overridden and
controlled through the SPI, as shown in Table 11. This register is
not changed by a Soft Reset.
TABLE 8. COARSE GAIN ADJUSTMENT
0x22[3:0] CoreA
0x26[3:0] CoreB
NOMINAL COARSE GAIN ADJUST
(%)
Bit3
+2.8
Bit2
+1.4
Bit1
-2.8
Bit0
-1.4
TABLE 9. MEDIUM AND FINE GAIN ADJUSTMENTS
CoreA
CoreB
PARAMETER
0x23[7:0]
0x29[7:0]
MEDIUM GAIN
0x24[7:0]
0x2A[7:0]
FINE GAIN
Steps
256
–Full Scale (0x00)
-2%
-0.20%
Mid–Scale (0x80)
0.00%
+Full Scale (0xFF)
+2%
+0.2%
Nominal Step Size
0.016%
0.0016%
TABLE 10. POWER-DOWN CONTROL
VALUE
0x25[2:0]
POWER DOWN MODE
000
Pin Control
001
Normal Operation
010
Nap Mode
100
Sleep Mode
TABLE 11. CLOCK DIVIDER SELECTION
VALUE
0x72[2:0]
CLOCK DIVIDER
000
Pin Control
001
Divide by 1
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