- 您现在的位置：买卖IC网 > PDF目录16743 > ISPPAC-POWR604-01TN44I (Lattice Semiconductor Corporation)IC ISP POWER MGR ANLG/LOG 44TQFP PDF资料下载
参数资料
| 型号： | ISPPAC-POWR604-01TN44I |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 13/30页 |
| 文件大小： | 0K |
| 描述： | IC ISP POWER MGR ANLG/LOG 44TQFP |
| 标准包装： | 160 |
| 系列： | ispPAC® |
| 应用： | 电源监控器，序列发生器 |
| 输入电压： | 0 V ~ 6 V |
| 电源电压： | 2.25 V ~ 5.5 V |
| 电流 - 电源： | 10mA |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 44-LQFP |
| 供应商设备封装： | 44-TQFP（10x10） |
| 包装： | 托盘 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页当前第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页
Lattice Semiconductor
ispPAC-POWR604 Data Sheet
to control the functional states of the sequencer state machine or other control or monitoring logic. The PLD AND
array shown in Figure 2-4 has 20 inputs and 41 product terms (PTs). The resources from the AND array feed the
eight macrocells. The resources within the macrocells share routing and contain a product-term allocation array.
The product term allocation array greatly expands the PLD’s ability to implement complex logical functions by
allowing logic to be shared between adjacent blocks and distributing the product terms to allow for wider decode
functions.
The basic macrocell has ?ve product terms that feed the OR gate and the ?ip-?op. The ?ip-?op in each macrocell is
independently con?gured. It can be programmed to function as a D-Type or T-Type ?ip-?op. The combinatorial func-
tions are achieved through the bypass MUX function shown. By having the polarity control XOR, the logic reduction
can be best ?t to minimize the number of product terms. The ?ip-?op’s clock drives from a common clock that can
be generated from a pre-scaled, on-board clock source or from an external clock. The macrocell also supports
asynchronous reset and preset functions, derived from product terms, the global reset input, or the power-on reset
signal.
Figure 2-3. ispPAC-POWR604 Macrocell Block Diagram
Global Reset
Power On Reset
Global Polarity Fuse for
Init Product-Term
Block Init Product-Term
Product-Term Allocation
PT4
PT3
PT2
PT1
PT0
R
D/T
P
Q
To ORP
Polarity
CLK
Clock
Macrocell Flip-Flop provides
D,T or Combinatorial
Output with Polarity
2-12
相关PDF资料 |
PDF描述 |
|---|---|
| 50TZV22M6.3X6.1 | CAP ALUM 22UF 50V 20% SMD |
| 400RX301R5M8X11.5 | CAP ALUM 1.5UF 400V 20% RADIAL |
| GMC07DRTN-S93 | CONN EDGECARD 14POS DIP .100 SLD |
| H2MXH-4036G | DIP CABLE - HDM40H/AE40G/X |
| UPB1A221MED1TD | CAP ALUM 220UF 10V 20% RADIAL |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ISPPAC-POWR60401TNE | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:In-System Programmable Power Supply Sequencing Controller and Monitor |
| ISPPAC-POWR60401TNI | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:In-System Programmable Power Supply Sequencing Controller and Monitor |
| ispPAC-POWR605-01SN24I | 功能描述:监控电路 PROCESSORPM 6-SUPPLY SUPERVISOR RESET GEN RoHS:否 制造商:STMicroelectronics 监测电压数: 监测电压: 欠电压阈值: 过电压阈值: 输出类型:Active Low, Open Drain 人工复位:Resettable 监视器:No Watchdog 电池备用开关:No Backup 上电复位延迟（典型值）:10 s 电源电压-最大:5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:UDFN-6 封装:Reel |
| ispPAC-POWR607-01N32I | 功能描述:监控电路 Prec. Prog. Pwr Sppl y Seq. Mon. I RoHS:否 制造商:STMicroelectronics 监测电压数: 监测电压: 欠电压阈值: 过电压阈值: 输出类型:Active Low, Open Drain 人工复位:Resettable 监视器:No Watchdog 电池备用开关:No Backup 上电复位延迟（典型值）:10 s 电源电压-最大:5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:UDFN-6 封装:Reel |
| ispPAC-POWR607-01NN32I | 功能描述:监控电路 Prec. Prog. Pwr Sppl y Seq. Mon. I RoHS:否 制造商:STMicroelectronics 监测电压数: 监测电压: 欠电压阈值: 过电压阈值: 输出类型:Active Low, Open Drain 人工复位:Resettable 监视器:No Watchdog 电池备用开关:No Backup 上电复位延迟（典型值）:10 s 电源电压-最大:5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:UDFN-6 封装:Reel |
发布紧急采购，3分钟左右您将得到回复。