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参数资料
| 型号： | ISPPAC-POWR604-01TN44I |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 21/30页 |
| 文件大小： | 0K |
| 描述： | IC ISP POWER MGR ANLG/LOG 44TQFP |
| 标准包装： | 160 |
| 系列： | ispPAC® |
| 应用： | 电源监控器，序列发生器 |
| 输入电压： | 0 V ~ 6 V |
| 电源电压： | 2.25 V ~ 5.5 V |
| 电流 - 电源： | 10mA |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 44-LQFP |
| 供应商设备封装： | 44-TQFP（10x10） |
| 包装： | 托盘 |
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Lattice Semiconductor
ispPAC-POWR604 Data Sheet
device type and version code (Figure 2-9). Access to the Identi?cation Register is immediately available, via a TAP
data scan operation, after power-up of the device, or by issuing a Test-Logic-Reset instruction. The bit code for this
instruction is de?ned by Lattice as shown in Table 2-4.
Figure 2-9. ID Code
MSB
LSB
XXXX / 0000 0001 0100 0001 / 0000 0100 001 / 1
Part Number
(16 bits)
0141h = ispPAC-POWR604
Version
(4 bits)
E 2 Configured
JEDEC Manufacturer
Identity Code for
Lattice Semiconductor
(11 bits)
Constant 1
(1 bit)
per 1149.1-1990
ispPAC-POWR604 Speci?c Instructions
There are 21 unique instructions speci?ed by Lattice for the ispPAC-PWR604. These instructions are primarily
used to interface to the various user registers and the E 2 CMOS non-volatile memory. Additional instructions are
used to control or monitor other features of the device. A brief description of each unique instruction is provided in
detail below, and the bit codes are found in Table 2-4.
ADDPLD – This instruction is used to set the address of the PLD AND/ARCH arrays for subsequent program or
read operations. This instruction also forces the outputs into the SAFESTATE.
DATAPLD – This instruction is used to shift PLD data into the register prior to programming or reading. This
instruction also forces the outputs into the SAFESTATE.
ERASEAND – This instruction will bulk erase the PLD AND array. The action occurs at the second rising edge of
TCK in Run-Test-Idle JTAG state. The device must already be in programming mode PROGRAMEN instruction).
This instruction also forces the outputs into the SAFESTATE.
ERASEARCH – This instruction will bulk erase the PLD ARCH array. The action occurs at the second rising edge
of TCK in Run-Test-Idle JTAG state. The device must already be in programming mode (PROGRAMEN instruction).
This instruction also forces the outputs into the SAFESTATE.
PROGPLD – This instruction programs the selected PLD AND/ARCH array column. The speci?c column is prese-
lected by using ADDPLD instruction. The programming occurs at the second rising edge of the TCK in Run-Test-
Idle JTAG state. The device must already be in programming mode (PROGRAMEN instruction) and operated at
3.3V to 5.0V. This instruction also forces the outputs into the SAFESTATE.
PROGESF – This instruction is used to program the electronic security fuse (ESF) bit. Programming the ESF bit
protects proprietary designs from being read out. The programming occurs at the second rising edge of the TCK in
Run-Test-Idle JTAG state. The device must already be in programming mode (PROGRAMEN instruction). This
instruction also forces the outputs into the SAFESTATE.
READPLD – This instruction is used to read the content of the selected PLD AND/ARCH array column. This spe-
ci?c column is preselected by using ADDPLD instruction. This instruction also forces the outputs into the SAF-
ESTATE.
DISCHARGE – This instruction is used to discharge the internal programming supply voltage after an erase or pro-
gramming cycle and prepares ispPAC-POWR604 for a read cycle. This instruction also forces the outputs into the
SAFESTATE.
2-20
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相关代理商/技术参数 |
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|---|---|
| ISPPAC-POWR60401TNE | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:In-System Programmable Power Supply Sequencing Controller and Monitor |
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| ispPAC-POWR605-01SN24I | 功能描述:监控电路 PROCESSORPM 6-SUPPLY SUPERVISOR RESET GEN RoHS:否 制造商:STMicroelectronics 监测电压数: 监测电压: 欠电压阈值: 过电压阈值: 输出类型:Active Low, Open Drain 人工复位:Resettable 监视器:No Watchdog 电池备用开关:No Backup 上电复位延迟（典型值）:10 s 电源电压-最大:5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:UDFN-6 封装:Reel |
| ispPAC-POWR607-01N32I | 功能描述:监控电路 Prec. Prog. Pwr Sppl y Seq. Mon. I RoHS:否 制造商:STMicroelectronics 监测电压数: 监测电压: 欠电压阈值: 过电压阈值: 输出类型:Active Low, Open Drain 人工复位:Resettable 监视器:No Watchdog 电池备用开关:No Backup 上电复位延迟（典型值）:10 s 电源电压-最大:5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:UDFN-6 封装:Reel |
| ispPAC-POWR607-01NN32I | 功能描述:监控电路 Prec. Prog. Pwr Sppl y Seq. Mon. I RoHS:否 制造商:STMicroelectronics 监测电压数: 监测电压: 欠电压阈值: 过电压阈值: 输出类型:Active Low, Open Drain 人工复位:Resettable 监视器:No Watchdog 电池备用开关:No Backup 上电复位延迟（典型值）:10 s 电源电压-最大:5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:UDFN-6 封装:Reel |
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