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| 型号： | KIT33887PNBEVB |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 33/37页 |
| 文件大小： | 0K |
| 描述： | KIT EVAL 33887 5A H-BRIDGE PQFN |
| 标准包装： | 1 |
| 主要目的： | 电源管理，H 桥驱动器（内部 FET） |
| 嵌入式： | 否 |
| 已用 IC / 零件： | MC33887 |
| 主要属性： | 5A 5 ~ 28V PWM 至 20kHz 有源电流限制 |
| 次要属性： | 故障状态，睡眠模式，比例电流镜像输出 |
| 已供物品： | 板，CD |
| 相关产品： | MC33887DWBR2-ND - IC H-BRIDGE 5A LOAD FDBK 54-SOIC MC33887VWR2-ND - IC H-BRIDGE 5.0A W/CS 20-HSOP MC33887PNBR2-ND - IC H-BRIDGE 5A CURR FDBK 36-PQFN MC33887PNB-ND - IC H-BRIDGE CURR FDBK 5A 36-PQFN MC33887DHR2-ND - IC H-BRIDGE 5A CURR FDBK 20-HSOP MC33887VW-ND - IC H-BRIDGE 5.0A W/CS 20-HSOP MC33887DWB-ND - IC H-BRIDGE 5.0A W/CS 54-SOIC MC33887DH-ND - IC H-BRIDGE 5.0A W/CS 20-HSOP |
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ADDITIONAL DOCUMENTATION
THERMAL ADDENDUM (REV 2.0)
ADDITIONAL DOCUMENTATION
33887HSOP
THERMAL ADDENDUM (REV 2.0)
Introduction
This thermal addendum is provided as a supplement to the MC33887 technical
data sheet. The addendum provides thermal performance information that may
be critical in the design and development of system applications. All electrical,
application, and packaging information is provided in the data sheet.
Packaging and Thermal Considerations
The MC33887 is offered in a 20 pin HSOP exposed pad, single die package.
There is a single heat source (P), a single junction temperature (T J ), and thermal
resistance (R θ JA ).
20-PIN
HSOP-EP
VW SUFFIX
98ASH70273A
20-PIN HSOP-EP
T J
=
R θ JA
.
P
The stated values are solely for a thermal performance comparison of one
package to another in a standardized environment. This methodology is not
meant to and will not predict the performance of a package in an application-
specific environment. Stated values were obtained by measurement and
simulation according to the standards listed below.
Standards
Note For package dimensions, refer to
the 33887 device data sheet.
Table 7.
Thermal Performance Comparison
Thermal Resistance
[ ° C/W]
20
1.0
1.0
6.0
0.2
0.2
NOTES:
R θ JA (1) , (4)
R θ JC (5)
52
1.0
* All measurements
are in millimeters
Soldermast
openings
1.Per JEDEC JESD51-2 at natural convection, still air condition.
2.2s2p thermal test board per JEDEC JESD51-5 and JESD51-7.
3.Per JEDEC JESD51-8, with the board temperature on the center
trace near the center lead.
4.Single layer thermal test board per JEDEC JESD51-3 and
20 Terminal HSOP-EP
1.27 mm Pitch
16.0 mm x 11.0 mm Body
12.2 mm x 6.9 mm Exposed Pad
Thermal vias
connected to top
buried plane
JESD51-5.
5.Thermal resistance between the die junction and the exposed
Figure 25. Thermal Land Pattern for Direct Thermal
Attachment According to JESD51-5
pad surface; cold plate attached to the package bottom side,
remaining surfaces insulated
33887
Analog Integrated Circuit Device Data
Freescale Semiconductor
33
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