- 您现在的位置：买卖IC网 > PDF目录11585 > KSZ8841-16MQL (Micrel Inc)IC MAC CTRLR 8/16BIT 128-PQFP PDF资料下载
参数资料
| 型号： | KSZ8841-16MQL |
| 厂商： | Micrel Inc |
| 文件页数： | 35/105页 |
| 文件大小： | 0K |
| 描述： | IC MAC CTRLR 8/16BIT 128-PQFP |
| 标准包装： | 66 |
| 控制器类型： | 以太网控制器，MAC |
| 接口： | 总线 |
| 电源电压： | 3.1 V ~ 3.5 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 128-BFQFP |
| 供应商设备封装： | 128-PQFP（14x20） |
| 包装： | 托盘 |
| 产品目录页面： | 1080 (CN2011-ZH PDF) |
| 配用： | 576-1631-ND - BOARD EVALUATION KSZ8841-16MQL |
| 其它名称： | 576-2112 KSZ8841-16MQL-ND |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页当前第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页
Micrel, Inc.
KSZ8841-16/32 MQL/MVL/MBL
October 2007
35
M9999-102207-1.6
Signal
Type
(1)
Function
For burst access: exactly like EXRDY signal in EISA to insert wait states. Note that
the wait states are inserted by system logic (memory) not by KSZ8841M.
BCLK
I
Bus Clock
Asynchronous Transfer Signals
RDN
I
Asynchronous Read
WRN
I
Asynchronous Write
ARDY
O
Asynchronous Ready
This signal is asserted (Low) to insert wait states.
Note 1: I = Input. O = Output. I/O = Bi-directional.
Table 2. Bus Interface Unit Signal Grouping
Regardless of whether the transfer is synchronous or asynchronous, if the address latch is required, use the rising edge of
ADSN to latch the incoming signals A[15:1], AEN, BE3N, BE2N, BE1N, and BE0N.
Note: If the local device decoder is used in either synchronous or asynchronous transfers, LDEVN will be asserted to
indicate that the KSZ8841M is successfully targeted. The signal LDEVN is a combinatorial decode of AEN and A[15:4].
Asynchronous Interface
For asynchronous transfers, the asynchronous dedicated signals RDN (for read) or WRN (for write) toggle, but the
synchronous dedicated signals CYCLEN, SWR, and RDYRTNN are de-asserted and stay at the same logic level
throughout the entire asynchronous transfer.
There is no data burst support for asynchronous transfer. All asynchronous transfers are single-data transfers. The BIU,
however, provides flexible asynchronous interfacing to communicate with various applications and architectures. Three
major ways of interfacing with the system (host) are.
1.
Interfacing with the system/host relying on local device decoding and having stable address throughout the whole
transfer: The typical example for this application is ISA-like bus interface using latched address signals as shown
in Figure 13. No additional address latch is required, therefore ADSN should be connected Low. The BIU decodes
A[15:4] and qualifies with AEN (Address Enable) to determine if the KSZ8841M device is the intended target. The
host utilizes the rising edge of RDN to latch read data and the BIU will use rising edge of WRN to latch write data.
Interfacing with the system/host relying on local device decoding but not having stable address throughout the entire
transfer: The typical example for this application is EISA-like bus (non-burst) interface as shown in the Figure 14. This
type of interface requires ADSN to latch the address on the rising edge. The BIU decodes latched A[15:4] and qualifies
with AEN to determine if the KSZ8841M device is the intended target. The data transfer is the same as the first case.
Interfacing with the system/host relying on central decoding (KSZ8841-32MQL only).
The typical example for this application is for an embedded processor having a central decoder on the system board or
within the processor. Connecting the chip select (CS) from system/host to DATACSN bypasses the local device decoder.
When the DATACSN is asserted, it only allows access to the Data Register in 32 bits and BE3N, BE2N, BE1N, and BE0N
are ignored as shown in the Figure 15. No other registers can be accessed by asserting DATACSN. The data transfer is
the same as in the first case. Independent of the type of asynchronous interface used. To insert a wait state, the BIU will
assert ARDY to prolong the cycle.
相关PDF资料 |
PDF描述 |
|---|---|
| PIC12CE518-04E/SM | IC MCU OTP 512X12 W/EE 8-SOIC |
| KSZ8895RQ | IC 10/100-T 5 PORT SW 128PQFP |
| PIC16LC620A-04/P | IC MCU OTP 512X14 COMP 18DIP |
| KSZ8863FLLI | IC ETHERNET SWITCH 3PORT 48-LQFP |
| PIC16C505-04E/SL | IC MCU OTP 1KX12 14SOIC |
相关代理商/技术参数 |
参数描述 |
|---|---|
| KSZ8841-16MQL A6 | 功能描述:IC MAC CTRLR 8/16BIT 128-PQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 控制器 系列:- 标准包装:4,900 系列:- 控制器类型:USB 2.0 控制器 接口:串行 电源电压:3 V ~ 3.6 V 电流 - 电源:135mA 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:36-VFQFN 裸露焊盘 供应商设备封装:36-QFN（6x6） 包装:* 其它名称:Q6396337A |
| KSZ8841-16MQL-EVAL | 功能描述:以太网开发工具 KSZ8841-16MQL Evaluation Board RoHS:否 制造商:Micrel 产品:Evaluation Boards 类型:Ethernet Transceivers 工具用于评估:KSZ8873RLL 接口类型:RMII 工作电源电压: |
| KSZ8841-16MVL | 功能描述:以太网 IC Single Ethernet Port + Generic (8, 16-bit) bus interface(Lead Free) RoHS:否 制造商:Micrel 产品:Ethernet Switches 收发器数量:2 数据速率:10 Mb/s, 100 Mb/s 电源电压-最大:1.25 V, 3.45 V 电源电压-最小:1.15 V, 3.15 V 最大工作温度:+ 85 C 封装 / 箱体:QFN-64 封装:Tray |
| KSZ8841-16MVL TR | 功能描述:以太网 IC Single Ethernet Port + Generic (8, 16-bit) bus interface(Lead Free) RoHS:否 制造商:Micrel 产品:Ethernet Switches 收发器数量:2 数据速率:10 Mb/s, 100 Mb/s 电源电压-最大:1.25 V, 3.45 V 电源电压-最小:1.15 V, 3.15 V 最大工作温度:+ 85 C 封装 / 箱体:QFN-64 封装:Tray |
| KSZ8841-16MVL-EVAL | 功能描述:BOARD EVALUATION KSZ8841-16MVL RoHS:是 类别:编程器，开发系统 >> 过时/停产零件编号 系列:- 标准包装:1 系列:- 类型:MCU 适用于相关产品:Freescale MC68HC908LJ/LK（80-QFP ZIF 插口） 所含物品:面板、缆线、软件、数据表和用户手册 其它名称:520-1035 |
发布紧急采购，3分钟左右您将得到回复。