参数资料
型号: KSZ8851-16MQL
厂商: Micrel Inc
文件页数: 26/88页
文件大小: 0K
描述: IC CTLR MAC/PHY NON-PCI 128-PQFP
产品培训模块: KSZ8851 10/100 Embedded Controllers
标准包装: 66
控制器类型: 以太网控制器,MAC/PHY
接口: 总线
电源电压: 1.8V,2.5V,3.3V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 128-BFQFP
供应商设备封装: 128-PQFP(14x20)
包装: 托盘
产品目录页面: 1081 (CN2011-ZH PDF)
配用: 576-3292-ND - BOARD EVALUATION KSZ8851-16MLL
其它名称: 576-3253
2009 Microchip Technology Inc.
DS39682E-page 31
PIC18F45J10 FAMILY
3.6.1
OSCILLATOR CONTROL REGISTER
The OSCCON register (Register 3-2) controls several
aspects of the device clock’s operation, both in
full-power operation and in power-managed modes.
The System Clock Select bits, SCS<1:0>, select the
clock source. The available clock sources are the
primary clock (defined by the FOSC<2:0> Configura-
tion bits), the secondary clock (Timer1 oscillator) and
the internal oscillator. The clock source changes after
one or more of the bits are written to, following a brief
clock transition interval.
The OSTS (OSCCON<3>) and T1RUN (T1CON<6>)
bits indicate which clock source is currently providing
the device clock. The OSTS bit indicates that the
Oscillator Start-up Timer (OST) has timed out and the
primary clock is providing the device clock in primary
clock modes. The T1RUN bit indicates when the
Timer1 oscillator is providing the device clock in sec-
ondary clock modes. In power-managed modes, only
one of these bits will be set at any time. If neither of
these bits is set, the INTRC is providing the clock, or
the internal oscillator has just started and is not yet
stable.
The IDLEN bit determines if the device goes into Sleep
mode or one of the Idle modes when the SLEEP
instruction is executed.
The use of the flag and control bits in the OSCCON
register is discussed in more detail in Section 4.0
3.6.1.1
System Clock Selection and the
FOSC2 Configuration Bit
The SCS bits are cleared on all forms of Reset. In the
device’s default configuration, this means the primary
oscillator defined by FOSC<1:0> (that is, one of the HC
or EC modes) is used as the primary clock source on
device Resets.
The default clock configuration on Reset can be changed
with the FOSC2 Configuration bit. The effect of this bit is
to set the clock source selected when SCS<1:0> = 00.
When FOSC2 = 1 (default), the oscillator source
defined by FOSC<1:0>
is selected whenever
SCS<1:0> = 00. When FOSC2 = 0, the INTRC oscillator
is selected whenever SCS<1:0> = 00. Because the SCS
bits are cleared on Reset, the FOSC2 setting also
changes the default oscillator mode on Reset.
Regardless of the setting of FOSC2, INTRC will always
be enabled on device power-up. It will serve as the
clock source until the device has loaded its configura-
tion values from memory. It is at this point that the
FOSC Configuration bits are read and the oscillator
selection of operational mode is made.
Note that either the primary clock or the internal
oscillator will have two bit setting options, at any given
time, depending on the setting of FOSC2.
3.6.2
OSCILLATOR TRANSITIONS
PIC18F45J10 family devices contain circuitry to
prevent clock “glitches” when switching between clock
sources. A short pause in the device clock occurs dur-
ing the clock switch. The length of this pause is the sum
of two cycles of the old clock source and three to four
cycles of the new clock source. This formula assumes
that the new clock source is stable.
Clock transitions are discussed in greater detail in
.
Note 1:
The Timer1 oscillator must be enabled to
select the secondary clock source. The
Timer1 oscillator is enabled by setting the
T1OSCEN bit in the Timer1 Control regis-
ter (T1CON<3>). If the Timer1 oscillator is
not enabled, then any attempt to select a
secondary clock source when executing a
SLEEP
instruction will be ignored.
2:
It is recommended that the Timer1
oscillator be operating and stable before
executing the SLEEP instruction or a very
long delay may occur while the Timer1
oscillator starts.
相关PDF资料
PDF描述
LTC4278CDKD#PBF IC PD IEEE 802.3AT 25.5W 32-DFN
KSZ8873MLL IC ETHERNET SWITCH 3PORT 64-LQFP
KSZ8863RLL IC ETHERNET SW 3PORT 48-LQFP
KSZ8863MLL IC ETHERNET SW 3PORT 48-LQFP
KSZ8863FLL IC ETHERNET SW 3PORT 48-LQFP
相关代理商/技术参数
参数描述
KSZ8851-16MQL-EVAL 功能描述:以太网开发工具 Single Ethernet Port + Generic (16-bit) Bus Interface(Lead Free) Eval Board RoHS:否 制造商:Micrel 产品:Evaluation Boards 类型:Ethernet Transceivers 工具用于评估:KSZ8873RLL 接口类型:RMII 工作电源电压:
KSZ8851-16MQLI 功能描述:以太网 IC Single Ethernet Port + Generic (16-bit) Bus Interface(Lead Free, I-Temp) RoHS:否 制造商:Micrel 产品:Ethernet Switches 收发器数量:2 数据速率:10 Mb/s, 100 Mb/s 电源电压-最大:1.25 V, 3.45 V 电源电压-最小:1.15 V, 3.15 V 最大工作温度:+ 85 C 封装 / 箱体:QFN-64 封装:Tray
KSZ8851-32MQL 功能描述:以太网 IC 10/100BT Ethernet MAC + PHY with Generic (32-bit) Bus Interface, Lead Free RoHS:否 制造商:Micrel 产品:Ethernet Switches 收发器数量:2 数据速率:10 Mb/s, 100 Mb/s 电源电压-最大:1.25 V, 3.45 V 电源电压-最小:1.15 V, 3.15 V 最大工作温度:+ 85 C 封装 / 箱体:QFN-64 封装:Tray
KSZ8851-32MQLI 功能描述:以太网 IC 10/100BT Ethernet MAC + PHY with Generic (32-bit) Bus Interface (I-Temp) RoHS:否 制造商:Micrel 产品:Ethernet Switches 收发器数量:2 数据速率:10 Mb/s, 100 Mb/s 电源电压-最大:1.25 V, 3.45 V 电源电压-最小:1.15 V, 3.15 V 最大工作温度:+ 85 C 封装 / 箱体:QFN-64 封装:Tray
KSZ8851MLL 制造商:MICREL 制造商全称:Micrel Semiconductor 功能描述:Single Port MAC/PHY Controller with Non PCI Interface