Micrel, Inc.
KSZ8873MLL/FLL/RLL
September 20, 2013
20
Revision 1.6
100BASE-FX Operation
100BASE-FX operation is similar to 100BASE-TX operation with the differences being that the scrambler/de-scrambler
and MLT3 encoder/decoder are bypassed on transmission and reception. In addition, auto-negotiation is bypassed and
auto MDI/MDI-X is disabled.
100BASE-FX Signal Detection
In 100BASE-FX operation, FXSD (fiber signal detect), input Pins 15 and 63, is usually connected to the fiber transceiver
SD (signal detect) output pin. The fiber signal threshold can be selected by Register 192 bit 7 and 6 respectively for port 2
and port 1, When FXSD is less than the threshold, no fiber signal is detected and a far-end fault (FEF) is generated.
When FXSD is over the threshold, the fiber signal is detected.
Alternatively, the designer may choose not to implement the FEF feature. In this case, the FXSD input pin is tied high to
force 100BASE-FX mode.
100BASE-FX signal detection is summarized in Table 1:
Table 1. FX Signal Threshold
Register 192 bit 7 (port 2), bit 6 (port 1)
Fiber Signal Threshold at FXSD
1
2.0V
0
1.2V
To ensure proper operation, a resistive voltage divider is recommended to adjust the fiber transceiver SD output voltage
swing to match the FXSD pin’s input voltage threshold.
100BASE-FX Far-End Fault
A far-end fault (FEF) occurs when the signal detection is logically false on the receive side of the fiber transceiver. The
KSZ8873FLL detects a FEF when its FXSD input is Fiber Signal Threshold. When a FEF is detected, the KSZ8873FLL
signals its fiber link partner that a FEF has occurred by sending 84 1’s followed by a zero in the idle period between
frames.
By default, FEF is enabled. FEF can be disabled through register setting.
10BASE-T Transmit
The 10BASE-T driver is incorporated with the 100BASE-TX driver to allow for transmission using the same magnetics.
They are internally wave-shaped and pre-emphasized into outputs with a typical 2.3V amplitude. The harmonic contents
are at least 27dB below the fundamental frequency when driven by an all-ones Manchester-encoded signal.
10BASE-T Receive
On the receive side, input buffers and level detecting squelch circuits are employed. A differential input receiver circuit and
a phase-locked loop (PLL) perform the decoding function. The Manchester-encoded data stream is separated into clock
signal and NRZ data. A squelch circuit rejects signals with levels less than 400mV or with short pulse widths to prevent
noise at the RXP-or-RXM input from falsely triggering the decoder. When the input exceeds the squelch limit, the PLL
locks onto the incoming signal and the KSZ8873MLL/FLL/RLL decodes a data frame. The receiver clock is maintained
active during idle periods in between data reception.
MDI/MDI-X Auto Crossover
To eliminate the need for crossover cables between similar devices, the KSZ8873MLL/FLL/RLL supports HP Auto
MDI/MDI-X and IEEE 802.3u standard MDI/MDI-X auto crossover. HP Auto MDI/MDI-X is the default.
The auto-sense function detects remote transmit and receive pairs and correctly assigns transmit and receive pairs for the
KSZ8873MLL/FLL/RLL device. This feature is extremely useful when end users are unaware of cable types, and also,
saves on an additional uplink configuration connection. The auto-crossover feature can be disabled through the port
control registers, or MIIM PHY registers.