Micrel, Inc.
KSZ8873MLL/FLL/RLL
September 20, 2013
32
Revision 1.6
Table 4. MII Signals
PHY-Mode Connections
MAC-Mode Connections
External MAC
Controller Signals
KSZ8873MLL/FL
PHY Signals
Pin Descriptions
External
PHY Signals
KSZ8873MLL/FLL
MAC Signals
MTXEN
SMTXEN3
Transmit enable
MTXEN
SMRXDV3
MTXER
SMTXER3
Transmit error
MTXER
(not used)
MTXD3
SMTXD33
Transmit data bit 3
MTXD3
SMRXD33
MTXD2
SMTXD32
Transmit data bit 2
MTXD2
SMRXD32
MTXD1
SMTXD31
Transmit data bit 1
MTXD1
SMRXD31
MTXD0
SMTXD30
Transmit data bit 0
MTXD0
SMRXD30
MTXC
SMTXC3
Transmit clock
MTXC
SMRXC3
MCOL
SCOL3
Collision detection
MCOL
SCOL3
MCRS
SCRS3
Carrier sense
MCRS
SCRS3
MRXDV
SMRXDV3
Receive data valid
MRXDV
SMTXEN3
MRXER
(not used)
Receive error
MRXER
SMTXER3
MRXD3
SMRXD33
Receive data bit 3
MRXD3
SMTXD33
MRXD2
SMRXD32
Receive data bit 2
MRXD2
SMTXD32
MRXD1
SMRXD31
Receive data bit 1
MRXD1
SMTXD31
MRXD0
SMRXD30
Receive data bit 0
MRXD0
SMTXD30
MRXC
SMRXC3
Receive clock
MRXC
SMTXC3
The MII operates in either PHY mode or MAC mode. The data interface is a nibble wide and runs at the network bit rate
(not encoded). Additional signals on the transmit side indicate when data is valid or when an error occurs during
transmission. Similarly, the receive side has signals that convey when the data is valid and without physical layer errors.
For half duplex operation, the SCOL signal indicates if a collision has occurred during transmission.
The KSZ8873MLL/FLL does not provide the MRXER signal for PHY mode operation and the MTXER signal for MAC
mode operation. Normally, MRXER indicates a receive error coming from the physical layer device and MTXER indicates
a transmit error from the MAC device. Since the switch filters error frames, these MII error signals are not used by the
KSZ8873MLL/FLL. So, for PHY mode operation, if the device interfacing with the KSZ8873MLL/FLL has an MRXER input
pin, it needs to be tied low. And, for MAC mode operation, if the device interfacing with the KSZ8873MLL/FLL has an
MTXER input pin, it also needs to be tied low.
The KSZ8873MLL/FLL provides a bypass feature in the MII PHY mode. Pin SMTXER3/MII_LINK is used for MII link
status. If the host is power down, Pin MII_LINK will go to high. In this case, no new ingress frames from port1 or port 2 will
be sent out through port 3, and the frames for port 3 already in packet memory will be flushed out.
RMII Interface Operation
The Reduced Media Independent Interface (RMII) specifies a low pin count Media Independent Interface (MII). RMII
provides a common interface between physical layer and MAC layer devices, and has the following key characteristics:
1.
Ports 10Mbps and 100Mbps data rates.
2.
Uses a single 50 MHz clock reference (provided internally or externally).
3.
Provides independent 2-bit wide (di-bit) transmit and receive data paths.
4.
Contains two distinct groups of signals: one for transmission and the other for reception
When EN_REFCLKO_3 is high, KSZ8873RLL will output a 50MHz in REFCLKO_3. Register 198 bit[3] is used to select
internal or external reference clock. Internal reference clock means that the clock for the RMII of KSZ8873RLL will be