参数资料
型号: KSZ8873MLL
厂商: Micrel Inc
文件页数: 64/115页
文件大小: 0K
描述: IC ETHERNET SWITCH 3PORT 64-LQFP
产品培训模块: KSZ8873 Ethernet Switches
特色产品: KSZ8873 Ethernet Switch Controller
标准包装: 160
控制器类型: 以太网开关控制器
接口: MII
电源电压: 1.8V,2.5V,3.3V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 64-LQFP
供应商设备封装: 64-LQFP(10x10)
包装: 托盘
产品目录页面: 1081 (CN2011-ZH PDF)
其它名称: 576-3459
Micrel, Inc.
KSZ8873MLL/FLL/RLL
September 20, 2013
52
Revision 1.6
PHY1 Register 29 (PHYAD = 0x1, REGAD = 0x1D): Not supported
PHY2 Register 29 (PHYAD = 0x2, REGAD = 0x1D): LinkMD Control/Status
Bit
Name
R/W
Description
Default
Reference
15
Vct_enable
R/W
(SC)
=1, Enable cable diagnostic. After VCT test
has completed, this bit will be self-cleared.
=0, Indicate cable diagnostic test (if enabled)
has completed and the status information is
valid for read.
0
Reg. 42, bit 4
14-13
Vct_result
RO
=00, Normal condition
=01, Open condition detected in cable
=10, Short condition detected in cable
=11, Cable diagnostic test has failed
00
Reg 42, bit[6:5]
12
Vct 10M Short
RO
=1, Less than 10 meter short
0
Reg. 42, bit 7
11-9
Reserved
RO
Reserved
000
8-0
Vct_fault_count
RO
Distance to the fault.
It’s approximately 0.4m*vct_fault_count[8:0]
{0, (0x00)}
{(Reg. 42, bit 0),
(Reg. 43, bit[7:0])}
PHY1 Register 31 (PHYAD = 0x1, REGAD = 0x1F): PHY Special Control/Status
PHY2 Register 31 (PHYAD = 0x2, REGAD = 0x1F): PHY Special Control/Status
Bit
Name
R/W
Description
Default
Reference
15-6
Reserved
RO
Reserved
{(0x00),00}
5
Polrvs
RO
=1, Polarity is reversed
=0, Polarity is not reversed
0
Reg. 31, bit 5
Reg. 47, bit 5
Note: This bit is
only valid for 10BT
4
MDI-X status
RO
=1, MDI
=0, MDI-X
0
Reg. 30, bit 7
Reg. 46, bit 7
3
Force_lnk
R/W
=1, Force link pass
=0, Normal Operation
0
Reg. 26, bit 3
Reg. 42, bit 3
2
Pwrsave
R/W
=0, Enable power saving
=1, Disable power saving
1
Reg. 26, bit 2
Reg. 42, bit 2
1
Remote
Loopback
R/W
=1, Perform Remote loopback, as follows:
Port 1 (reg. 26, bit 1 = ‘1’)
Start: RXP1/RXM1 (port 1)
Loopback: PMD/PMA of port 1’s PHY
End: TXP1/TXM1 (port 1)
Port 2 (reg. 42, bit 1 = ‘1’)
Start: RXP2/RXM2 (port 2)
Loopback: PMD/PMA of port 2’s PHY
End: TXP2/TXM2 (port 2)
=0, Normal Operation
0
Reg. 26, bit 1
Reg. 42, bit 1
0
Reserved
R/W
Reserved
Do not change the default value.
0
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