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参数资料
型号： KSZ8873MLL
厂商： Micrel Inc
文件页数： 44/115页
文件大小： 0K
描述： IC ETHERNET SWITCH 3PORT 64-LQFP
产品培训模块： KSZ8873 Ethernet Switches
特色产品： KSZ8873 Ethernet Switch Controller
标准包装： 160
控制器类型： 以太网开关控制器
接口： MII
电源电压： 1.8V，2.5V，3.3V
工作温度： 0°C ~ 70°C
安装类型： 表面贴装
封装/外壳： 64-LQFP
供应商设备封装： 64-LQFP（10x10）
包装： 托盘
产品目录页面： 1081 (CN2011-ZH PDF)
其它名称： 576-3459
Micrel, Inc.
KSZ8873MLL/FLL/RLL
September 20, 2013
34
Revision 1.6
The KSZ8873RLL filters error frames, and thus does not implement the RX_ER output signal. To detect error frames from
RMII PHY devices, the SMTXER3 input signal of the KSZ8873RLL is connected to the RXER output signal of the RMII
PHY device.
Collision detection is implemented in accordance with the RMII Specification.
In RMII mode, tie MII signals, SMTXD3[3:2] and SMTXER3, to ground if they are not used.
The KSZ8873RLL RMII can interface with RMII PHY and RMII MAC devices. The latter allows two KSZ8873RLL devices
to be connected back-to-back. Table 7 shows the KSZ8873RLL RMII pin connections with an external RMII PHY and an
external RMII MAC, such as another KSZ8873RLL device.
Table 7. RMII Signal Connections
KSZ8873RLL PHY-MAC Connections
KSZ8873RLL MAC-MAC
Connections
External PHY Signals
KSZ8873RLL
MAC Signals
Pin Descriptions
KSZ8873RLL
MAC Signals
External
MAC Signals
REF_CLK
REFCLKI_3
Reference Clock
REFCLKI_3
REF_CLK
TX_EN
SMRXDV3
Carrier sense/
Receive data valid
SMRXDV3
CRS_DV
TXD1
SMRXD31
Receive data bit 1
SMRXD31
RXD1
TXD0
SMRXD30
Receive data bit 0
SMRXD30
RXD0
CRS_DV
SMTXEN3
Transmit enable
SMTXEN3
TX_EN
RXD1
SMTXD31
Transmit data bit 1
SMTXD31
TXD1
RXD0
SMTXD30
Transmit data bit 0
SMTXD30
TXD0
RX_ER
SMTXER3
Receive error
(not used)
MII Management (MIIM) Interface
The KSZ8873MLL/FLL/RLL supports the IEEE 802.3 MII Management Interface, also known as the Management Data
Input/Output (MDIO) Interface. This interface allows upper-layer devices to monitor and control the states of the
KSZ8873MLL/FLL/RLL. An external device with MDC/MDIO capability is used to read the PHY status or configure the
PHY settings. Further detail on the MIIM interface is found in Clause 22.2.4.5 of the IEEE 802.3u Specification and refer
to 802.3 section 22.3.4 for the timing.
The MIIM interface consists of the following:
A physical connection that incorporates the data line (SDA_MDIO) and the clock line (SCL_MDC).
A specific protocol that operates across the aforementioned physical connection that allows an external controller to
communicate with the KSZ8873MLL/FLL/RLL device.
Access to a set of eight 16-bit registers, consisting of six standard MIIM registers [0:5] and two custom MIIM registers
[29, 31].
The MIIM Interface can operate up to a maximum clock speed of 5MHz.
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相关代理商/技术参数
参数描述
KSZ8873MLL AM 功能描述:以太网 IC 3-Port 10/100 Ethernet Switch with 1x MII Interface (Automotive Grade, Lead Free) RoHS:否 制造商:Micrel 产品:Ethernet Switches 收发器数量:2 数据速率:10 Mb/s, 100 Mb/s 电源电压-最大:1.25 V, 3.45 V 电源电压-最小:1.15 V, 3.15 V 最大工作温度:+ 85 C 封装 / 箱体:QFN-64 封装:Tray
KSZ8873MLL AM TR 功能描述:以太网 IC 3-Port 10/100 Ethernet Switch with 1x MII Interface (Automotive Grade, Lead Free) RoHS:否 制造商:Micrel 产品:Ethernet Switches 收发器数量:2 数据速率:10 Mb/s, 100 Mb/s 电源电压-最大:1.25 V, 3.45 V 电源电压-最小:1.15 V, 3.15 V 最大工作温度:+ 85 C 封装 / 箱体:QFN-64 封装:Tray
KSZ8873MLL/8863MLL 制造商:Micrel Inc 功能描述:EVAL BOARD
KSZ8873MLL_09 制造商:MICREL 制造商全称:Micrel Semiconductor 功能描述:Integrated 3-Port 10/100 Managed Switch with PHYs
KSZ8873MLL_11 制造商:MICREL 制造商全称:Micrel Semiconductor 功能描述:Integrated 3-Port 10/100 Managed Switch with PHYs
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