参数资料
型号: KSZ8873MLL
厂商: Micrel Inc
文件页数: 97/115页
文件大小: 0K
描述: IC ETHERNET SWITCH 3PORT 64-LQFP
产品培训模块: KSZ8873 Ethernet Switches
特色产品: KSZ8873 Ethernet Switch Controller
标准包装: 160
控制器类型: 以太网开关控制器
接口: MII
电源电压: 1.8V,2.5V,3.3V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 64-LQFP
供应商设备封装: 64-LQFP(10x10)
包装: 托盘
产品目录页面: 1081 (CN2011-ZH PDF)
其它名称: 576-3459
Micrel, Inc.
KSZ8873MLL/FLL/RLL
September 20, 2013
82
Revision 1.6
Register 156[6:0] (0x9C): Port 1 Q2 Egress Data Rate Limit
Register 160[6:0] (0xA0): Port 2 Q2 Egress Data Rate Limit
Register 164[6:0] (0xA4): Port 3 Q2 Egress Data Rate Limit
Bit
Name
R/W
Description
Default
7
Reserved
R/W
Reserved
Do not change the default values.
0
6-0
Q2 Egress
Data Rate limit
R/W
Egress data rate limit for priority 2 frames
Egress traffic from this priority queue is shaped according to the Data Rate
Limit Table.
0
Register 157[6:0] (0x9D): Port 1 Q3 Egress Data Rate Limit
Register 161[6:0] (0xA1): Port 2 Q3 Egress Data Rate Limit
Register 165[6:0] (0xA5): Port 3 Q3 Egress Data Rate Limit
Bit
Name
R/W
Description
Default
7
Reserved
R/W
Reserved
Do not change the default values.
0
6-0
Q3 Egress
Data Rate limit
R/W
Egress data rate limit for priority 3 frames
Egress traffic from this priority queue is shaped according to the Data Rate
Limit Table.
0
Register 166 (0xA6): KSZ8873 Mode Indicator
Bit
Name
RO
Description
Default
7-0
KSZ8873
Mode Indicator
RO
bit7: 1: 2 MII mode
bit6: 1: 48P pkg of 2 PHY mode
bit5: 1: Reserved
0: Reserved
bit4: 1: Port 3 RMII
0: Port 3 MII
bit3: 1: Reserved
0: Reserved
bit2: 1: Port 3 MAC MII
0: Port 3 PHY MII
bit1: 1: Port 1 Copper
0: Port 1 Fiber
bit0: 1: Port 2 Copper
0: Port 2 Fiber
0x03 MLL
0x13 RLL
0x00FLL
Register 167 (0xA7): High-Priority Packet Buffer Reserved for Q3
Bit
Name
RW
Description
Default
7-0
Reserved
RO
Reserved
Do not change the default values.
0x45
Register 168 (0xA8): High-Priority Packet Buffer Reserved for Q2
Bit
Name
RW
Description
Default
7-0
Reserved
RO
Reserved
Do not change the default values.
0x35
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