参数资料
型号: L6740L
厂商: STMICROELECTRONICS
元件分类: 模拟信号调理
英文描述: SPECIALTY ANALOG CIRCUIT, PQFP48
封装: 7 X 7 MM, 1 MM HEIGHT, HTQFP-48
文件页数: 18/44页
文件大小: 755K
代理商: L6740L
L6740L
Output voltage positioning
Figure 10.
Current reading - CORE section (left) and NB section (right)
The current read through the CSx+ / CSx- pairs is converted into a current IINFOx propor-
tional to the current delivered by each phase and the information about the average current
IAVG = ΣIINFOx / N is internally built into the device (N is the number of working phases). The
error between the read current IINFOx and the reference IAVG is then converted into a voltage
that with a proper gain is used to adjust the duty cycle whose dominant value is set by the
voltage error amplifier in order to equalize the current carried by each phase.
6.3
CORE section - load-line and load-indicator (optional)
L6740L is able to introduce a dependence of the output voltage on the load current
recovering part of the drop due to the output capacitor ESR in the load transient. Introducing
a dependence of the output voltage on the load current, a static error, proportional to the
output current, causes the output voltage to vary according to the sensed current.
Figure 10 shows the Current Sense Circuit used to implement the Load-Line. The current
flowing across the inductor(s) is read through the R - C filter across CSx+ and CSx- pins. RG
programs a trans conductance gain and generates a current ICSx proportional to the current
of the phase. The sum of the ICSx current is then sourced by the FB pin (IDROOP). RFB gives
the final gain to program the desired load-line slope (Figure 9).
Time constant matching between the inductor (L / DCR) and the current reading filter (RC)
is required to implement a real equivalent output impedance of the system so avoiding over
and/or under shoot of the output voltage as a consequence of a load transient. See
Section 6.2. The output characteristic vs. load current is then given by (Offset disabled):
Where RLL is the resulting load-line resistance implemented by the CORE section.
The whole power supply can be then represented by a “real” voltage generator with an
equivalent output resistance RLL and a voltage value of VID.
RFB resistor can be then designed according to the RLL specifications as follow:
Caution:
Load-line (DROOP) implementation is optional, in case it is not desired, the resulting current
information may be employed for other purposes, such as an additional load indicator (LI). In
NB_ISEN
I
NB
Lx
CSx+
CSx-
DCRx
R
C
RG
RISEN
I
PHASEx
NB Current Sense across LS Mosfet
VDD Inductor DCR Current Sense
INB_ISEN
ICSx-=IINFOx
From
ext Driver
V
OUT
V
CORE
VID
R
FB
I
DROOP
VID
R
FB
DCR
R
G
------------- I
OUT
VID
R
LL
I
OUT
==
=
R
FB
R
LL
R
G
DCR
-------------
=
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