参数资料
型号: L6740L
厂商: STMICROELECTRONICS
元件分类: 模拟信号调理
英文描述: SPECIALTY ANALOG CIRCUIT, PQFP48
封装: 7 X 7 MM, 1 MM HEIGHT, HTQFP-48
文件页数: 26/44页
文件大小: 755K
代理商: L6740L
Output voltage monitoring and protections
L6740L
Permanently sets the PWM of the non-involved section to HiZ while keeping
ENDRV of the non-involved section low in order to realize an HiZ condition of the
non-involved section.
Drives the OSC/ FLT pin high.
Power supply or EN pin cycling is required to restart operations.
The OV threshold needs to be programmed through the OVP pin. Connecting the OVP pin
to SGND through a resistor ROVP, the OVP threshold becomes the voltage present at the
pin. Since the OVP pin sources a constant IOVP=11 μA current, the programmed voltage
becomes:
=>
Filter OVP pin with 100 pF(max) to SGND.
7.2
Feedback disconnection
L6740L provides both CORE and NB sections with FB Disconnection protection. This fea-
ture acts in order to stop the device from regulating dangerous voltages in case the remote
sense connections are left floating. The protection is available for both the sections and
operates for both the positive and negative sense.
According to Figure 13, the protection works as follow:
CORE section:
Positive sense is performed monitoring the CORE output voltage through both VSEN
and CS1-. As soon as CS1- is more than 600 mV higher than VSEN, the device latches
with all PWMx set to HiZ and ENDRVx set to zero. FLT pin is driven high. A 30
μA
pull-down current on the VSEN forces the device to detect this fault condition.
Negative sense is performed monitoring the internal opamp used to recover the SGND
losses by comparing its output and the internal reference generated by the DAC. As
soon as the difference between the output and the input of this opamp is higher than
500 mV, the device latches with all PWMx set to HiZ and ENDRVx set to zero. FLT pin
is driven high.
NB section (SVI only)
Positive sense is performed sourcing a 50
μA current that pulls-up the NB_VSEN pin in
order to force the device to detect an OV condition for the NB section.
Negative sense is performed monitoring the internal opamp used to recover the SGND
losses by comparing its output and the internal reference generated by the DAC. As
soon as the difference between the output and the input of this opamp is higher than
500 mV, the device latches with all PWMx set to HiZ and ENDRVx set to zero. FLT pin
is driven high.
To recover from a latch condition, cycle VCC or EN.
OVP
TH
R
OVP
11
μA
=
R
OVP
TH
11
μA
--------------------
=
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