参数资料
型号: L6740L
厂商: STMICROELECTRONICS
元件分类: 模拟信号调理
英文描述: SPECIALTY ANALOG CIRCUIT, PQFP48
封装: 7 X 7 MM, 1 MM HEIGHT, HTQFP-48
文件页数: 2/44页
文件大小: 755K
代理商: L6740L
Pins description and connection diagrams
L6740L
19
Cor
e
section
CS4+
Channel 4 current sense positive input. Connect through an R-C filter to
the phase-side of the channel 4 inductor. When working at 2 or 3
phase, directly connect to Vout_CORE.
See Section 9 for proper layout of this connection.
20
CS4-
Channel 4 current sense negative input. Connect through a RG resistor
to the output-side of the channel inductor. When working at 2 or 3
phase, connect through RG to CS4+.
See Section 9 for proper layout of this connection.
21
OC_PHASE
Per-phase over-current (CORE section).
Internally set to 1.24 V, connecting to SGND with a resistor ROC_TH it
programs the OC threshold per-phase. See Section 7.4.1 for details.
22
NC
Not internally connected.
23
NB
section
NB_ISEN
NB current sense pin.
Used for NB voltage positioning and NB_OCP. Connect through a
resistor RISEN to the relative LS Drain. See Section 7.4 for details.
24
NC
Not internally connected.
25,
26
PVI
interf
a
c
e
VID4, VID5
Voltage IDentification pins.
Internally pulled-low by 10
μA, they are used to program the output
voltage. Used only in PVI-mode, ignored when in SVI-mode.
See Section 5 for details.
27
OSC / FLT
OSC: It allows programming the switching frequency FSW of both
sections. Switching frequency can be increased according to the
resistor ROSC connected from the pin to. SGND with a gain of
6.8 kHz/A (see Section 8 for details). If floating, the switching
frequency is 150 kHz per phase.
FLT: The pin is forced high (3.3 V) in case of an OV / UV fault. To
recover from this condition, cycle VCC or the EN pin. See Section 7 for
details.
28
Core
s
e
ction
OC_AVG /
LI
Average over-current and load indicator pin.
A current proportional to the current delivered by the CORE section (a
copy of the DROOP current) is sourced through this pin.
The average-OC threshold is programmed by connecting a resistor
ROC_AVG to SGND. When the generated voltage crosses the OC_AVG
threshold (VOC_AVGTH = 2.5 V Typ) the device latches with all mosfets
OFF (to recover, cycle VCC or the EN pin).
A load indicator with 2.5 V end-of-scale is then implemented.
See Section 7.4.1 for details.
29
NB
section
NB_OS
Offset programming pin.
Internally set to 1.24 V, connecting a ROS_NB resistor to SGND allows
setting a current that is mirrored into NB_FB pin in order to program a
positive offset according to the selected RFB_NB. Short to SGND to
disable the function. See Section 6.7 for details.
30
NB_FBG
Remote ground sense.
Connect to the negative side of the load to perform remote sense. See
Section 9 for proper layout of this connection.
Table 2.
Pin description (continued)
Pin#
Name
Function
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