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参数资料
| 型号： | LC74950BG |
| 厂商： | SANYO SEMICONDUCTOR CO LTD |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA96 |
| 封装： | 6 X 6 MM, FBGA-96 |
| 文件页数： | 18/37页 |
| 文件大小： | 350K |
| 代理商： | LC74950BG |
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LC74950BG
No.A1647-25/37
2) ADC
Registers related to ADC control
Name
Functions
Sub address
bit width
STBL_Y
STBL_B
STBL_R
These registers control the ADC standby mode (Y: STBL_Y, B: STBL_B, R: STBL_R).
0000: ADC standby mode
1111: ADC normal operating mode
*1: Any other settings than above inhibited.
*2: This must be set in line with the operating mode of ADC.
0x21
0x23
0x25
4
ICNT_Y
ICNT_B
ICNT_R
These registers control the internal bias current of ADC (Y: ICNT_Y, B: ICNT_B,
R: ICNT_R).
Bias current generating resistor values:
000: 600
Ω (recommended)
001: 540
Ω
010: 480
Ω
011: 420
Ω
100: 360
Ω
101: 300
Ω
110: 240
Ω
111: 180
Ω
0x39
0x3A
0x3B
3
7. Digital Clamp
1) Digital clamp pulses
Registers related to digital clamp pulse control
Name
Functions
Sub address
bit width
OSEL
This register sets the digital clamp pulse output to ON or OFF.
It is used to adjust the position of the digital clamp pulses.
000: Normal operation
101: The Y digital clamp pulse is output from the YGOUT7 pin and the C digital clamp
pulse is output from the CBOUT7 pin.
0x2E
3
DCLPYON
DCLPCON
These registers set the digital clamp pulse to ON and OFF
(Y: DCLPYON, C: DCLPCON).
0: OFF, 1: ON
0x0A
0x0F
1
DCPYSET
DCPCSET
These registers set the digital clamp pulse positions (Y: DCPYSET, C: DCPCSET).
They are set in 4-clock increments using the trailing edge of Hsync as a reference.
Setting range: -32 (00h) to +31 (3Fh), default value: +/-0 (20h)
0x0A
0x0F
6
DCLPYW
DCLPCW
These set the digital clamp pulse width. It can be set in 1 clock increments.
0 specifies a pulse width of 0.
(Y: DCLPYW, C: DCLPCW)
0x0B
0x10
6
DCLPYV
DCLPCV
These registers set the disable function of the digital clamp pulses during the vertical
blanking period to ON or OFF.
(Y: DCLPYV, C: DCLPCV)
0: OFF, 1: ON
0x0B
0x10
1
DCPYVMS
DCPCVMS
These specify the start line at which the digital clamp pulses are enabled within 1V.
As a basic rule, the same values as the V-enable start line (VBLKS[10:0]) are set.
0x0C-0x0D
0x11-0x12
11
DCPYVME
DCPCVME
These specify the end line at which the digital clamp pulses are enabled within 1V.
As a basic rule, the same values as the V-enable end line (VBLKS[10:0]) are set.
0x0C-0x0E
0x11-0x13
11
Digital clamp pulse settings (how to output the clamp pulses)
OSEL[2:0] *1
YGOUT7
CBOUT7
101
Digital clamp pulse (Y)
Digital clamp pulse (C)
*1: The "000" setting must be used during normal operation.
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