参数资料
型号: LC74950BG
厂商: SANYO SEMICONDUCTOR CO LTD
元件分类: 消费家电
英文描述: SPECIALTY CONSUMER CIRCUIT, PBGA96
封装: 6 X 6 MM, FBGA-96
文件页数: 6/37页
文件大小: 350K
代理商: LC74950BG
LC74950BG
No.A1647-14/37
5) ADC/PLL independent mode <2>
(External clock input, PLL configured separately: CLKOUT1=CLKIN, CLKOUT2=CLKIN/In-Divide*Out-Divide)
Example: Component (ADC down sample), PLL: Generation of separate system clock
4. Clock system
1) Clock system diagram
*1 Explanation of signals
FOUT:
A clock generated in the PLL circuit and synchronized with the reference signal (FIN). The frequency of
FIN and PLL divider value (HPLDIV, 28h-29h, bits 15-0) determine the frequency of FOUT.
FOUTX2:
A clock generated in the PLL circuit and synchronized with the reference signal (FIN). The frequency of
FOUTX2 is two times of the frequency of FOUT.
CLKOUT:
A clock generated in the ADC. To output the clock it is necessary to adjust the phase of the sampling clock
(CLKADC) in order that the rising edge of the clock does not occur near the change point of the ADC
sampled data.
CLKADCINV
00h, bit2-0
FOUT *1
FOUTX2 *1
CLKSEL
00h, bit3
1/2
Divider
PLL
CLKSEL
00h, bit2-0
3
/
3
/
C
CLKOUT2INV
00h, bit7
CLKOUT1INV
00h, bit6
CLKOUT *1
CLKOUTINV
01h, bit7
CLKOUT2 *2
CLKOUT1
*2
CLKIN
POWERIN
CLKINDIV
CLKSEL
40h, bit5-0
00h, bit4
CLKININV
00h, bit2-0
03h, bit3
HSINV
/
6
1/1 to 1/64
Divider
HSIN
FIN
logic
ADC
CLKADC
*2
I
2C
G/Y
B/Cb
R/Cr
8
R OUT
B OUT
G OUT
Digital
Clamp
Gain
Offset
HS OUT
VS OUT
DE OUT
CLKOUT1
VS IN
PDOWN
CLKOUT2
33MHz
CKGEN
RESET
13.5MHz
HS IN
CLK IN (13.5MHz)
PLL
S
E
L
S
E
L
1/2
S
E
L
LC74950ADC
ADC
Analog Self-
clamping
Timing
Generator
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