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参数资料
| 型号： | LC74950BG |
| 厂商： | SANYO SEMICONDUCTOR CO LTD |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA96 |
| 封装： | 6 X 6 MM, FBGA-96 |
| 文件页数： | 9/37页 |
| 文件大小： | 350K |
| 代理商： | LC74950BG |
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LC74950BG
No.A1647-17/37
Continued from preceding page.
Name
Functions
Sub address
bit width
PLLGAIN
This register switches the setting of Fmin, Fmax, and Gain of the H-lock PLL VCO.
000: Fmin=60MHz, Fmax=240MHz, Gain=120MHz/V←Standard setting
001: Fmin=Standard, Fmax=Standard-20%, Gain=Standard-22.5%
010: Fmin=Standard-20%, Fmax=Standard, Gain=Standard+2.5%
011: Fmin=Standard-20%, Fmax=Standard-20%, Gain=Standard-20.0%
100: Fmin=Standard+20%, Fmax=Standard+10%, Gain=Standard+8.75%
101: Fmin=Standard+20%, Fmax=Standard-10%, Gain=Standard-13.75%
110: Fmin=Standard, Fmax=Standard+10%, Gain=Standard+11.25%
111: Fmin=Standard, Fmax=Standard-10%, Gain=Standard-11.25%
* After changing the setting, an interval of 3.0ms is required for the H-lock PLL to get
stabilized.
0x27
3
PLLCTL2
H-lock PLL power down mode
0: Normal operation
1: H-lock PLL power OFF
0x27
1
PLLCTL1
H-lock PLL Normal Mode FOUT Disable
0: Normal operation
1: H-lock PLL output= L fixed
0x27
1
CPIS_COAST
CPIS_ORG
These registers set the PLL charge pump constant current
(make sure that CPIS_COAST=CPIS_ORG)
0000: 40
μA
0001: 60
μA
0010: 120
μA
0011: 180
μA
0100: 200
μA
0110: 280
μA
0101: 300
μA
1000: 360
μA
0111: 420
μA
1010: 440
μA ←Standard setting
1100: 520
μA
1001: 540
μA
1110: 600
μA
1011: 660
μA
1101: 780
μA
1111: 900
μA
* After changing the setting, an interval of 3.0ms is required for the H-lock PLL to get
stabilized.
0x2A
4
PLL setting example (when using as H-lock PLL)
Ref
[kHz]
CLKSEL
[2:0]
PLLDIV
15-12
PLLDIV
11-0
FVCO*
[MHz]
FOUTX2
[MHz]
FOUT
[MHz]
CPIS
[3:0]
PLLGAIN
[2:0]
NTSC
15.734
2h
3h
6B2h
216
(54)
27
Ch
0h
NTSC
15.734
2h
7h
358h
216
27
13.5
Ch
0h
PAL
15.630
2h
3h
6BEh
216
(54)
27
Ch
0h
PAL
15.630
2h
7h
35Eh
216
27
13.5
Ch
0h
PAL-N
15.630
2h
7h
35Eh
216
27
13.5
Ch
0h
PAL-M
15.734
2h
7h
358h
216
27
13.5
Ch
0h
QVGA
15.70
2h
Fh
1A6h
213
13.3
6.68
Ch
0h
VGA
31.5
2h
3h
31Eh
201
(50.4)
25.2
Ch
0h
WVGA
31.0
2h
3h
41Eh
262
(65.4)
32.7
Dh
0h
*20MHz < FVCO < 340MHz
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