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参数资料
型号： LCMXO640C-4F256I
厂商： LATTICE SEMICONDUCTOR CORP
元件分类： PLD
中文描述： FLASH PLD, 4.2 ns, PBGA256
封装： 17 X 17 MM, FPBGA-256
文件页数： 12/95页
文件大小： 867K
代理商： LCMXO640C-4F256I
April 2006
Data Sheet
2006 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specications and information herein are subject to change without notice.
www.latticesemi.com
1-1
Introduction_01.2
Features
■ Non-volatile, Innitely Recongurable
Instant-on – powers up in microseconds
Single chip, no external conguration memory
required
Excellent design security, no bit stream to
intercept
Recongure SRAM based logic in milliseconds
SRAM and non-volatile memory programmable
through JTAG port
Supports background programming of
non-volatile memory
■ Sleep Mode
Allows up to 100x static current reduction
■ TransFR Reconguration (TFR)
In-eld logic update while system operates
■ High I/O to Logic Density
256 to 2280 LUT4s
73 to 271 I/Os with extensive package options
Density migration supported
Lead free/RoHS compliant packaging
■ Embedded and Distributed Memory
Up to 27.6 Kbits sysMEM Embedded Block
RAM
Up to 7.5 Kbits distributed RAM
Dedicated FIFO control logic
■ Flexible I/O Buffer
Programmable sysIO buffer supports wide
range of interfaces:
LVCMOS 3.3/2.5/1.8/1.5/1.2
LVTTL
PCI
LVDS, Bus-LVDS, LVPECL, RSDS
■ sysCLOCK PLLs
Up to two analog PLLs per device
Clock multiply, divide, and phase shifting
■ System Level Support
IEEE Standard 1149.1 Boundary Scan
Onboard oscillator
Devices operate with 3.3V, 2.5V, 1.8V or 1.2V
power supply
IEEE 1532 compliant in-system programming
Introduction
The MachXO is optimized to meet the requirements of
applications traditionally addressed by CPLDs and low
capacity FPGAs: glue logic, bus bridging, bus interfac-
ing, power-up control, and control logic. These devices
bring together the best features of CPLD and FPGA
devices on a single chip.
Table 1-1. MachXO Family Selection Guide
Device
LCMXO256
LCMXO640
LCMXO1200
LCMXO2280
LUTs
256
640
1200
2280
Dist. RAM (Kbits)
2.0
6.0
6.25
7.5
EBR SRAM (Kbits)
0
9.2
27.6
Number of EBR SRAM Blocks (9 Kbits)
0013
VCC Voltage
1.2/1.8/2.5/3.3V
Number of PLLs
0012
Max. I/O
78
159
211
271
Packages
100-pin TQFP (14x14 mm)
78
74
73
144-pin TQFP (20x20 mm)
113
100-ball csBGA (8x8 mm)
78
74
132-ball csBGA (8x8 mm)
101
256-ball ftBGA/fpBGA (17x17 mm)
159
1
211
324-ball ftBGA (19x19 mm)
271
1. fpBGA package
MachXO Family Data Sheet
Introduction
相关PDF资料
PDF描述
LCMXO640C-5F256C
LCN0402T-9N0H-N 1 ELEMENT, 0.009 uH, CERAMIC-CORE, GENERAL PURPOSE INDUCTOR, SMD
LCN0402T-9N0G-N 1 ELEMENT, 0.009 uH, CERAMIC-CORE, GENERAL PURPOSE INDUCTOR, SMD
LCN0402T-8N2H-N 1 ELEMENT, 0.0082 uH, CERAMIC-CORE, GENERAL PURPOSE INDUCTOR, SMD
LCN0402T-8N2G-N 1 ELEMENT, 0.0082 uH, CERAMIC-CORE, GENERAL PURPOSE INDUCTOR, SMD
相关代理商/技术参数
参数描述
LCMXO640C-4FN256C 功能描述:CPLD - 复杂可编程逻辑器件 Use LCMXO640C-4FTN25 RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100
LCMXO640C-4FN256I 功能描述:CPLD - 复杂可编程逻辑器件 Use LCMXO640C-4FTN25 RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100
LCMXO640C-4FT256C 功能描述:CPLD - 复杂可编程逻辑器件 640 LUTs 159 IO 1.8/ 2.5/3.3V -4 Spd RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100
LCMXO640C-4FT256I 功能描述:CPLD - 复杂可编程逻辑器件 640 LUTs 159 IO 1.8/ 2.5/3.3V -4 Spd I RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100
LCMXO640C-4FTN256C 功能描述:CPLD - 复杂可编程逻辑器件 640 LUTs 159 IO 1.8/ 2.5/3.3V -4 Spd RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100
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