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参数资料
型号： LCMXO640C-4F256I
厂商： LATTICE SEMICONDUCTOR CORP
元件分类： PLD
中文描述： FLASH PLD, 4.2 ns, PBGA256
封装： 17 X 17 MM, FPBGA-256
文件页数： 18/95页
文件大小： 867K
代理商： LCMXO640C-4F256I
2-22
Architecture
Lattice Semiconductor
MachXO Family Data Sheet
Device Conguration
All MachXO devices contain a test access port that can be used for device conguration and programming.
The non-volatile memory in the MachXO can be congured in two different modes:
In IEEE 1532 mode via the IEEE 1149.1 port. In this mode, the device is off-line and I/Os are controlled by
BSCAN registers.
In background mode via the IEEE 1149.1 port. This allows the device to remain operational in user mode
while reprogramming takes place.
The SRAM conguration memory can be congured in three different ways:
At power-up via the on-chip non-volatile memory.
After a refresh command is issued via the IEEE 1149.1 port.
In IEEE 1532 mode via the IEEE 1149.1 port.
Figure 2-22 provides a pictorial representation of the different programming modes available in the MachXO
devices. On power-up, the SRAM is ready to be congured with IEEE 1149.1 serial TAP port using IEEE 1532 pro-
tocols.
Leave Alone I/O
When using IEEE 1532 mode for non-volatile memory programming, SRAM conguration, or issuing a refresh
command, users may specify I/Os as high, low, tristated or held at current value. This provides excellent exibility
for implementing systems where reconguration or reprogramming occurs on-the-y.
TransFR (Transparent Field Reconguration)
TransFR (TFR) is a unique Lattice technology that allows users to update their logic in the eld without interrupting
system operation using a single ispVM command. See Lattice technical note #TN1087, Minimizing System Inter-
ruption During Conguration Using TransFR Technology, for details.
Security
The MachXO devices contain security bits that, when set, prevent the readback of the SRAM conguration and
non-volatile memory spaces. Once set, the only way to clear the security bits is to erase the memory space.
For more information on device conguration, please see details of additional technical documentation at the end
of this data sheet.
相关PDF资料
PDF描述
LCMXO640C-5F256C
LCN0402T-9N0H-N 1 ELEMENT, 0.009 uH, CERAMIC-CORE, GENERAL PURPOSE INDUCTOR, SMD
LCN0402T-9N0G-N 1 ELEMENT, 0.009 uH, CERAMIC-CORE, GENERAL PURPOSE INDUCTOR, SMD
LCN0402T-8N2H-N 1 ELEMENT, 0.0082 uH, CERAMIC-CORE, GENERAL PURPOSE INDUCTOR, SMD
LCN0402T-8N2G-N 1 ELEMENT, 0.0082 uH, CERAMIC-CORE, GENERAL PURPOSE INDUCTOR, SMD
相关代理商/技术参数
参数描述
LCMXO640C-4FN256C 功能描述:CPLD - 复杂可编程逻辑器件 Use LCMXO640C-4FTN25 RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100
LCMXO640C-4FN256I 功能描述:CPLD - 复杂可编程逻辑器件 Use LCMXO640C-4FTN25 RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100
LCMXO640C-4FT256C 功能描述:CPLD - 复杂可编程逻辑器件 640 LUTs 159 IO 1.8/ 2.5/3.3V -4 Spd RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100
LCMXO640C-4FT256I 功能描述:CPLD - 复杂可编程逻辑器件 640 LUTs 159 IO 1.8/ 2.5/3.3V -4 Spd I RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100
LCMXO640C-4FTN256C 功能描述:CPLD - 复杂可编程逻辑器件 640 LUTs 159 IO 1.8/ 2.5/3.3V -4 Spd RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100
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