- 您现在的位置：买卖IC网 > PDF目录15611 > LFM34INTPU1A (Freescale Semiconductor)ADAPTER MPC5534 324-BGA PDF资料下载
参数资料
| 型号： | LFM34INTPU1A |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 14/60页 |
| 文件大小： | 0K |
| 描述： | ADAPTER MPC5534 324-BGA |
| 标准包装： | 1 |
| 模块/板类型： | 适配器板 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页当前第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页
Electrical Characteristics
MPC5534 Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
21
19
CLKOUT period jitter, measured at fSYS max:
13, 14
Peak-to-peak jitter (clock edge to clock edge)
Long term jitter (averaged over a 2 ms interval)
CJITTER
—
5.0
0.01
%
fCLKOUT
20
Frequency modulation range limit 15
(do not exceed fsys maximum)
CMOD
0.8
2.4
%fSYS
21
ICO frequency
fico = [ fref_crystal (MFD + 4) ] (PREDIV + 1)
16
fico = [ fref_ext (MFD + 4) ] (PREDIV + 1)
fico
48
8017
MHz
22
Predivider output frequency (to PLL)
fPREDIV
420 18
MHz
1 Nominal crystal and external reference values are worst-case not more than 1%. The device operates correctly if the frequency
remains within ± 5% of the specification limit. This tolerance range allows for a slight frequency drift of the crystals over time.
The designer must thoroughly understand the drift margin of the source clock.
2 All internal registers retain data at 0 Hz.
3 Up to the maximum frequency rating of the device (refer to Table 1).
4 Loss of reference frequency is defined as the reference frequency detected internally, which transitions the PLL into self-clocked
mode.
5 The PLL operates at self-clocked mode (SCM) frequency when the reference frequency falls below f
LOR. SCM frequency is
measured on the CLKOUT ball with the divider set to divide-by-two of the system clock.
NOTE: In SCM, the MFD and PREDIV have no effect and the RFD is bypassed.
6 Use the EXTAL input high voltage parameter when using the FlexCAN oscillator in crystal mode (no quartz crystals or
resonators). (Vextal – Vxtal) must be 400 mV for the oscillator’s comparator to produce the output clock.
7 Use the EXTAL input low voltage parameter when using the FlexCAN oscillator in crystal mode (no quartz crystals or
resonators). (Vxtal –Vextal) must be 400 mV for the oscillator’s comparator to produce the output clock.
8 I
xtal is the oscillator bias current out of the XTAL pin with both EXTAL and XTAL pins grounded.
9 C
PCB_EXTAL and CPCB_XTAL are the measured PCB stray capacitances on EXTAL and XTAL, respectively.
10 This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits in the
synthesizer control register (SYNCR). From power up with crystal oscillator reference, the lock time also includes the crystal
startup time.
11 PLL is operating in 1:1 PLL mode.
12 V
DDE = 3.0–3.6 V.
13 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f
sys.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the PLL circuitry via VDDSYN and VSSSYN and variation in crystal oscillator frequency increase the jitter percentage
for a given interval. CLKOUT divider is set to divide-by-two.
14 Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of (jitter + Cmod).
15 Modulation depth selected must not result in f
sys value greater than the fsys maximum specified value.
16 f
sys = fico (2
RFD).
17 The ICO frequency can be higher than the maximum allowable system frequency. For this case, set the FMPLL synthesizer
control register reduced frequency divider (FMPLL_SYNCR[RFD]) to divide-by-two (RFD = 0b001). Therefore, for a 40 MHz
maximum device (system frequency), program the FMPLL to generate 80 MHz at the ICO output and then divide-by-two the
RFD to provide the 40 MHz clock.
18 Maximum value for dual controller (1:1) mode is (f
MAX 2) with the predivider set to 1 (FMPLL_SYNCR[PREDIV] = 0b001).
Table 12. FMPLL Electrical Specifications (continued)
(VDDSYN = 3.0–3.6 V; VSS = VSSSYN = 0.0 V; TA = TL to TH)
Spec
Characteristic
Symbol
Minimum
Maximum
Unit
相关PDF资料 |
PDF描述 |
|---|---|
| EEM28DTKT-S288 | CONN EDGECARD 56POS .156 EXTEND |
| ADM6318CY46ARJZ-R7 | IC SUPERVISOR W/RESET SOT23-5 |
| PCG0J471MCL1GS | CAP ALUM 470UF 6.3V 20% SMD |
| MAX6442KAOSTD3+T | IC BATTERY MON DUAL SOT23-8 |
| VI-BW3-EY-F2 | CONVERTER MOD DC/DC 24V 50W |
相关代理商/技术参数 |
参数描述 |
|---|---|
| LFM-39A | 制造商:Leader 功能描述: |
| LFM53INTPU1A | 功能描述:IC 与器件插座 MPC5553 324-PIN BGA TO P RoHS:否 制造商:Molex 产品:LGA Sockets 节距:1.02 mm 排数: 位置/触点数量:2011 触点电镀:Gold 安装风格:SMD/SMT 端接类型:Solder 插座/封装类型:LGA 2011 工作温度范围:- 40 C to + 100 C |
| LFM53INTPWA | 功能描述:IC 与器件插座 MPC5553 416-PIN BGA TO P RoHS:否 制造商:Molex 产品:LGA Sockets 节距:1.02 mm 排数: 位置/触点数量:2011 触点电镀:Gold 安装风格:SMD/SMT 端接类型:Solder 插座/封装类型:LGA 2011 工作温度范围:- 40 C to + 100 C |
| LFM54INTPWA | 功能描述:插座和适配器 PB-FREE MPC5554 BGA TO P RoHS:否 制造商:Silicon Labs 产品:Adapter 用于:EM35x |
| LFM65INTPU1A | 功能描述:插座和适配器 PBSN MPC5565 324 BGA TO RoHS:否 制造商:Silicon Labs 产品:Adapter 用于:EM35x |
发布紧急采购，3分钟左右您将得到回复。