- 您现在的位置：买卖IC网 > PDF目录15611 > LFM34INTPU1A (Freescale Semiconductor)ADAPTER MPC5534 324-BGA PDF资料下载
参数资料
| 型号： | LFM34INTPU1A |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 5/60页 |
| 文件大小： | 0K |
| 描述： | ADAPTER MPC5534 324-BGA |
| 标准包装： | 1 |
| 模块/板类型： | 适配器板 |
第1页第2页第3页第4页当前第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页
Electrical Characteristics
MPC5534 Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
13
3.7.1
Input Value of Pins During POR Dependent on VDD33
When powering up the device, VDD33 must not lag the latest VDDSYN or RESET power pin (VDDEH6) by
more than the VDD33 lag specification listed in Table 6, spec 8. This avoids accidentally selecting the
bypass clock mode because the internal versions of PLLCFG[0:1] and RSTCFG are not powered and
therefore cannot read the default state when POR negates. VDD33 can lag VDDSYN or the RESET power
pin (VDDEH6), but cannot lag both by more than the VDD33 lag specification. This VDD33 lag specification
applies during power up only. VDD33 has no lead or lag requirements when powering down.
3.7.2
Power-Up Sequence (VRC33 Grounded)
The 1.5 V VDD power supply must rise to 1.35 V before the 3.3 V VDDSYN power supply and the RESET
power supply rises above 2.0 V. This ensures that digital logic in the PLL for the 1.5 V power supply does
not begin to operate below the specified operation range lower limit of 1.35 V. Because the internal 1.5 V
POR is disabled, the internal 3.3 V POR or the RESET power POR must hold the device in reset. Since
they can negate as low as 2.0 V, VDD must be within specification before the 3.3 V POR and the RESET
POR negate.
Figure 3. Power-Up Sequence (VRC33 Grounded)
3.7.3
Power-Down Sequence (VRC33 Grounded)
The only requirement for the power-down sequence with VRC33 grounded is if VDD decreases to less than
its operating range, VDDSYN or the RESET power must decrease to less than 2.0 V before the VDD power
increases to its operating range. This ensures that the digital 1.5 V logic, which is reset only by an ORed
POR and can cause the 1.5 V supply to decrease less than its specification value, resets correctly. See
Table 6, footnote 1.
VDDSYN and RESET Power
VDD
2.0 V
1.35 V
VDD must reach 1.35 V before VDDSYN and the RESET power reach 2.0 V
相关PDF资料 |
PDF描述 |
|---|---|
| EEM28DTKT-S288 | CONN EDGECARD 56POS .156 EXTEND |
| ADM6318CY46ARJZ-R7 | IC SUPERVISOR W/RESET SOT23-5 |
| PCG0J471MCL1GS | CAP ALUM 470UF 6.3V 20% SMD |
| MAX6442KAOSTD3+T | IC BATTERY MON DUAL SOT23-8 |
| VI-BW3-EY-F2 | CONVERTER MOD DC/DC 24V 50W |
相关代理商/技术参数 |
参数描述 |
|---|---|
| LFM-39A | 制造商:Leader 功能描述: |
| LFM53INTPU1A | 功能描述:IC 与器件插座 MPC5553 324-PIN BGA TO P RoHS:否 制造商:Molex 产品:LGA Sockets 节距:1.02 mm 排数: 位置/触点数量:2011 触点电镀:Gold 安装风格:SMD/SMT 端接类型:Solder 插座/封装类型:LGA 2011 工作温度范围:- 40 C to + 100 C |
| LFM53INTPWA | 功能描述:IC 与器件插座 MPC5553 416-PIN BGA TO P RoHS:否 制造商:Molex 产品:LGA Sockets 节距:1.02 mm 排数: 位置/触点数量:2011 触点电镀:Gold 安装风格:SMD/SMT 端接类型:Solder 插座/封装类型:LGA 2011 工作温度范围:- 40 C to + 100 C |
| LFM54INTPWA | 功能描述:插座和适配器 PB-FREE MPC5554 BGA TO P RoHS:否 制造商:Silicon Labs 产品:Adapter 用于:EM35x |
| LFM65INTPU1A | 功能描述:插座和适配器 PBSN MPC5565 324 BGA TO RoHS:否 制造商:Silicon Labs 产品:Adapter 用于:EM35x |
发布紧急采购，3分钟左右您将得到回复。