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| 型号： | LM25119PSQX |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | 稳压器 |
| 英文描述： | DUAL SWITCHING CONTROLLER, QCC32 |
| 封装： | 5 X 5 MM, LLP-32 |
| 文件页数： | 10/24页 |
| 文件大小： | 694K |
| 代理商： | LM25119PSQX |
30126259
FIGURE 7. Feedback Configuration
UVLO DIVIDER
The UVLO threshold is internally set to 1.25V at the UVLO
pin. The LM25119 is enabled when the system input voltage
VIN causes the UVLO pin to exceed the threshold voltage of
1.25V. When the UVLO pin voltage is below the threshold, the
internal 20
μA current source is disabled. When the UVLO pin
voltage exceeds the 1.25V threshold, the 20
μA current source
is enabled causing the UVLO pin voltage to increase, provid-
ing hysteresis. The values of R
UV1 and RUV2 can be deter-
mined from the following equation:
(34)
(35)
V
HYS is the desired UVLO hysteresis at VIN, and VIN in the
second equation is the desired UVLO release (turn-on) volt-
age. For example, if it is desired for the LM25119 to be
enabled when VIN reaches 5.6V, and the desired hysteresis
is 1.05V, then R
UV2 should be set to 52.5k and RUV1 should
be set to 15.1k
. For this application R
UV2 was selected to be
52.3k
, R
UV1was selected to be 15k. The LM25119 can be
remotely shutdown by taking the UVLO pin below 0.4V with
an external open collector or open drain device. The outputs
and the VCC regulator are disabled in shutdown mode. Ca-
pacitor C
FT provides filtering for the divider. A value of 100pF
was chosen for C
FT. The voltage at the UVLO pin should nev-
er exceed 15V when using the external set-point divider. It
may be necessary to clamp the UVLO pin at high input volt-
ages.
30126257
FIGURE 8. UVLO Configuration
MOSFET SELECTION
Selection of the power MOSFETs is governed by the same
tradeoffs as switching frequency. Breaking down the losses
in the high-side and low-side MOSFETs is one way to com-
pare the relative efficiencies of different devices. When using
discrete SO-8 MOSFETs, generally the output current capa-
bility range is 2A to 10A. Losses in the power MOSFETs can
be broken down into conduction loss, gate charging loss, and
switching loss. Conduction loss P
DC is approximately:
(36)
(37)
Where, D is the duty cycle and the factor of 1.3 accounts for
the increase in MOSFET on-resistance due to heating. Alter-
natively, the factor of 1.3 can be eliminated and the high
temperature on-resistance of the MOSFET can be estimated
using the R
DS(ON) vs Temperature curves in the MOSFET
datasheet. Gate charging loss, P
GC, results from the current
driving the gate capacitance of the power MOSFETs and is
approximated as:
(38)
Where Q
g refers to the total gate charge of an individual
MOSFET, and ‘n’ is the number of MOSFETs. Gate charge
loss differs from conduction and switching losses in that the
actual dissipation occurs in the LM25119 and not in the MOS-
FET itself. Further loss in the LM25119 is incurred if the gate
driving current is supplied by the internal linear regulator.
Switching loss occurs during the brief transition period as the
MOSFET turns on and off. During the transition period both
current and voltage are present in the channel of the MOS-
FET. The switching loss can be approximated as:
(39)
Where t
R and tF are the rise and fall times of the MOSFET.
The rise and fall times are usually mentioned in the MOSFET
datasheet or can be empirically observed with an oscillo-
scope. Switching loss is calculated for the high-side MOSFET
only. Switching loss in the low-side MOSFET is negligible be-
cause the body diode of the low-side MOSFET turns on
before the MOSFET itself, minimizing the voltage from drain
to source before turn-on. For this example, the maximum
drain-to-source voltage applied to either MOSFET is 36V.The
selected MOSFETs must be able to withstand 36V plus any
ringing from drain to source, and be able to handle at least
the VCC voltage plus any ringing from gate to source. A good
choice of MOSFET for the 36V input design example is the
SI7884. It has an R
DS(ON) of 7.5m and total gate charge of
21nC. In applications where a high step-down ratio is main-
tained in normal operation, efficiency may be optimized by
choosing a high-side MOSFET with lower Q
g, and low-side
MOSFET with lower R
DS(ON).
MOSFET SNUBBER
A resistor-capacitor snubber network across the low-side
MOSFET reduces ringing and spikes at the switching node.
Excessive ringing and spikes can cause erratic operation and
couple noise to the output. Selecting the values for the snub-
ber is best accomplished through empirical methods. First,
make sure the lead lengths for the snubber connections are
very short. Start with a resistor value between 5 and 50
.
Increasing the value of the snubber capacitor results in more
damping, but higher snubber losses. Select a minimum value
for the snubber capacitor that provides adequate damping of
www.national.com
18
LM25119
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相关代理商/技术参数 |
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| LM25119PSQX/NOPB | 功能描述:DC/DC 开关控制器 RoHS:否 制造商:Texas Instruments 输入电压:6 V to 100 V 开关频率: 输出电压:1.215 V to 80 V 输出电流:3.5 A 输出端数量:1 最大工作温度:+ 125 C 安装风格: 封装 / 箱体:CPAK |
| LM25119QPSQ/NOPB | 制造商:Texas Instruments 功能描述: 制造商:Texas Instruments 功能描述:IC REG CTRLR BUCK PWM CM 32-LLP 制造商:Texas Instruments 功能描述:LM25119QPSQ/NOPB |
| LM25119QPSQX/NOPB | 制造商:Texas Instruments 功能描述:IC REG CTRLR BUCK PWM CM 32-LLP 制造商:Texas Instruments 功能描述:Dual Synchronous Buck Controller |
| LM2512 | 制造商:NSC 制造商全称:National Semiconductor 功能描述:Mobile Pixel Link Level 0, 24-Bit RGB Display Interface Serializer with Dithering and Look Up Table Option |
| LM-2512 | 制造商:ROHM 制造商全称:Rohm 功能描述:16 x 32 matrix display |
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