参数资料
型号: LM25119PSQX
厂商: NATIONAL SEMICONDUCTOR CORP
元件分类: 稳压器
英文描述: DUAL SWITCHING CONTROLLER, QCC32
封装: 5 X 5 MM, LLP-32
文件页数: 11/24页
文件大小: 694K
代理商: LM25119PSQX
the spikes on the switch waveform at high load. A snubber
may not be necessary with an optimized layout.
ERROR AMPLIFIER COMPENSATION
R
COMP, CCOMP and CHF configure the error amplifier gain
characteristics to accomplish a stable voltage loop gain. One
advantage of current mode control is the ability to close the
loop with only two feedback components, R
COMP and CCOMP.
The voltage loop gain is the product of the modulator gain and
the error amplifier gain. For the 3.3V output design example,
the modulator is treated as an ideal voltage-to-current con-
verter. The DC modulator gain of the LM25119 can be mod-
eled as:
(40)
Note that A is the gain of the current sense amplifier which is
10 in the LM25119. The dominant low frequency pole of the
modulator is determined by the load resistance (R
LOAD) and
output capacitance (C
OUT). The corner frequency of this pole
is:
(41)
For R
LOAD = 3.3V / 8A = 0.413 and COUT = 724μF (effective)
then f
P(MOD) = 532Hz
DC Gain
(MOD) = 0.413 / (10 x 8m) = 5.16 = 14.2dB
For the 3.3V design example, the modulator gain vs. frequen-
cy characteristic is shown in Figure 9.
30126216
FIGURE 9. Modulator Gain and Phase
Components R
COMP and CCOMP configure the error amplifier
as a Type II configuration. The DC gain of the amplifier is
80dB with a pole at 0Hz and a zero at f
ZEA = 1 / (2π x
R
COMP x CCOMP). The error amplifier zero cancels the modu-
lator pole leaving a single pole response at the crossover
frequency of the voltage loop. A single pole response at the
crossover frequency yields a very stable loop with 90 degrees
of phase margin. For the design example, a conservative tar-
get loop bandwidth (crossover frequency) of 11kHz was se-
lected. The compensation network zero (f
ZEA) should be
selected at least an order of magnitude less than the target
crossover frequency. This constrains the product of R
COMP
and C
COMP for a desired compensation network zero 1 / (2π
x R
COMP x CCOMP) to be about 1.1kHz. Increasing RCOMP,
while proportionally decreasing C
COMP, increases the error
amp gain. Conversely, decreasing R
COMP while proportionally
increasing C
COMP, decreases the error amp gain. For the de-
sign example C
COMP was selected as 6800pF and RCOMP was
selected as 36.5k
. These values configure the compensa-
tion network zero at 640Hz. The error amp gain at frequencies
greater than f
ZEA is: RCOMP / RFB2, which is approximately 5.22
(14.3dB).
30126217
FIGURE 10. Error Amplifier Gain and Phase
The overall voltage loop gain can be predicted as the sum (in
dB) of the modulator gain and the error amp gain.
30126218
FIGURE 11. Overall Voltage Loop Gain and Phase
If a network analyzer is available, the modulator gain can be
measured and the error amplifier gain can be configured for
the desired loop transfer function. If the K factor is between 2
and 3, the stability should be checked with the network ana-
lyzer. If a network analyzer is not available, the error amplifier
compensation components can be designed with the guide-
lines given. Step load transient tests can be performed to
verify acceptable performance. The step load goal is mini-
mum overshoot with a damped response. C
HF can be added
to the compensation network to decrease noise susceptibility
of the error amplifier. The value of C
HF must be sufficiently
small since the addition of this capacitor adds a pole in the
19
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LM25119
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